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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-07-14 14:07:02 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-07-14 20:19:59 -0500 |
| commit | 7f9f4347cf325c63a39fe30910f3fb211ae2cc15 (patch) | |
| tree | fa1cf8a170572b65af737680b1000d0324099c60 /include/post.h | |
| parent | e5852787f0c3c442a276262f13d91ca450605ac0 (diff) | |
| download | u-boot-imx-7f9f4347cf325c63a39fe30910f3fb211ae2cc15.zip u-boot-imx-7f9f4347cf325c63a39fe30910f3fb211ae2cc15.tar.gz u-boot-imx-7f9f4347cf325c63a39fe30910f3fb211ae2cc15.tar.bz2 | |
85xx: Add some L1/L2 SPR register definitions
Add new L1/L2 SPRs related to e500mc cache config and control.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/post.h')
0 files changed, 0 insertions, 0 deletions