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authorSimon Glass <sjg@chromium.org>2016-01-18 20:19:15 -0700
committerBin Meng <bmeng.cn@gmail.com>2016-01-24 12:07:17 +0800
commit9d731c82f0b17ea31666b23e5685d3d2a8388a68 (patch)
tree632fdce6062043157524d4a08bbc0613c08c1267 /include/pci.h
parenta6eb93b3212d37fe623ed3b4351eedb971c12e3c (diff)
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dm: pci: Add a function to write a BAR
Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'include/pci.h')
-rw-r--r--include/pci.h17
1 files changed, 15 insertions, 2 deletions
diff --git a/include/pci.h b/include/pci.h
index cb2562f..d0d152c 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -757,7 +757,9 @@ extern void pci_mpc85xx_init (struct pci_controller *hose);
/**
* pci_write_bar32() - Write the address of a BAR including control bits
*
- * This writes a raw address (with control bits) to a bar
+ * This writes a raw address (with control bits) to a bar. This can be used
+ * with devices which require hard-coded addresses, not part of the normal
+ * PCI enumeration process.
*
* @hose: PCI hose to use
* @dev: PCI device to update
@@ -765,7 +767,7 @@ extern void pci_mpc85xx_init (struct pci_controller *hose);
* @addr: BAR address with control bits
*/
void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
- u32 addr_and_ctrl);
+ u32 addr);
/**
* pci_read_bar32() - read the address of a bar
@@ -1167,6 +1169,17 @@ int pci_get_regions(struct udevice *dev, struct pci_region **iop,
struct pci_region **memp, struct pci_region **prefp);
/**
+ * dm_pci_write_bar32() - Write the address of a BAR
+ *
+ * This writes a raw address to a bar
+ *
+ * @dev: PCI device to update
+ * @barnum: BAR number (0-5)
+ * @addr: BAR address
+ */
+void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
+
+/**
* dm_pci_read_bar32() - read a base address register from a device
*
* @dev: Device to check