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| author | Zang Roy-R61911 <tie-fei.zang@freescale.com> | 2013-07-04 07:25:03 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:41 -0700 |
| commit | 7b4e58440f7813a952133e77f2d9c4a475730e40 (patch) | |
| tree | 9d2082e2063031e51b07ea1f040d35c3263accb0 /include/pci.h | |
| parent | 0795eff34c5744dcc59ead6edbbcd2cd600f58fe (diff) | |
| download | u-boot-imx-7b4e58440f7813a952133e77f2d9c4a475730e40.zip u-boot-imx-7b4e58440f7813a952133e77f2d9c4a475730e40.tar.gz u-boot-imx-7b4e58440f7813a952133e77f2d9c4a475730e40.tar.bz2 | |
powerpc/pcie: add PCIe version 3.x support
T4240 PCIe IP is version 3.0 and has some update comparing previous
QorIQ products.
1. Move Freescale specific register define
to
arch/powerpc/include/asm/fsl_pci.h
and update the register offset define for T4240.
2. add the status/control register define
use status/control register to judge the link status
3. The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is RC or EP mode.
This patch fixes the PCIe card link up issue on T4240QDS.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/pci.h')
| -rw-r--r-- | include/pci.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/include/pci.h b/include/pci.h index 01002a4..911ba89 100644 --- a/include/pci.h +++ b/include/pci.h @@ -410,13 +410,6 @@ #define PCI_MAX_PCI_DEVICES 32 #define PCI_MAX_PCI_FUNCTIONS 8 -#define PCI_DCR 0x54 /* PCIe Device Control Register */ -#define PCI_DSR 0x56 /* PCIe Device Status Register */ -#define PCI_LSR 0x5e /* PCIe Link Status Register */ -#define PCI_LCR 0x5c /* PCIe Link Control Register */ -#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ -#define PCI_LTSSM_L0 0x16 /* L0 state */ - /* Include the ID list */ #include <pci_ids.h> |