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| author | Stefan Roese <sr@denx.de> | 2008-06-03 20:19:08 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-06-03 20:19:08 +0200 |
| commit | 10a3367955bc2033b288915f8f10d0e507fe2fa1 (patch) | |
| tree | c3ac82364df83db5d5cb963c64b863b77a20445c /include/ns9750_mem.h | |
| parent | 97f7d27c8ecf34879d6b747c10fa9a18c02a4cc0 (diff) | |
| parent | 1f1554841a4c8e069d331176f0c3059fb2bb8280 (diff) | |
| download | u-boot-imx-10a3367955bc2033b288915f8f10d0e507fe2fa1.zip u-boot-imx-10a3367955bc2033b288915f8f10d0e507fe2fa1.tar.gz u-boot-imx-10a3367955bc2033b288915f8f10d0e507fe2fa1.tar.bz2 | |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'include/ns9750_mem.h')
| -rw-r--r-- | include/ns9750_mem.h | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/include/ns9750_mem.h b/include/ns9750_mem.h index 44c8ddc..666e412 100644 --- a/include/ns9750_mem.h +++ b/include/ns9750_mem.h @@ -35,23 +35,23 @@ /* the register addresses */ -#define NS9750_MEM_CTRL (0x0000) -#define NS9750_MEM_STATUS (0x0004) -#define NS9750_MEM_CFG (0x0008) -#define NS9750_MEM_DYN_CTRL (0x0020) -#define NS9750_MEM_DYN_REFRESH (0x0024) +#define NS9750_MEM_CTRL (0x0000) +#define NS9750_MEM_STATUS (0x0004) +#define NS9750_MEM_CFG (0x0008) +#define NS9750_MEM_DYN_CTRL (0x0020) +#define NS9750_MEM_DYN_REFRESH (0x0024) #define NS9750_MEM_DYN_READ_CFG (0x0028) -#define NS9750_MEM_DYN_TRP (0x0030) -#define NS9750_MEM_DYN_TRAS (0x0034) -#define NS9750_MEM_DYN_TSREX (0x0038) -#define NS9750_MEM_DYN_TAPR (0x003C) -#define NS9750_MEM_DYN_TDAL (0x0040) -#define NS9750_MEM_DYN_TWR (0x0044) -#define NS9750_MEM_DYN_TRC (0x0048) -#define NS9750_MEM_DYN_TRFC (0x004C) -#define NS9750_MEM_DYN_TXSR (0x0050) -#define NS9750_MEM_DYN_TRRD (0x0054) -#define NS9750_MEM_DYN_TMRD (0x0058) +#define NS9750_MEM_DYN_TRP (0x0030) +#define NS9750_MEM_DYN_TRAS (0x0034) +#define NS9750_MEM_DYN_TSREX (0x0038) +#define NS9750_MEM_DYN_TAPR (0x003C) +#define NS9750_MEM_DYN_TDAL (0x0040) +#define NS9750_MEM_DYN_TWR (0x0044) +#define NS9750_MEM_DYN_TRC (0x0048) +#define NS9750_MEM_DYN_TRFC (0x004C) +#define NS9750_MEM_DYN_TXSR (0x0050) +#define NS9750_MEM_DYN_TRRD (0x0054) +#define NS9750_MEM_DYN_TMRD (0x0058) #define NS9750_MEM_STAT_EXT_WAIT (0x0080) #define NS9750_MEM_DYN_CFG_BASE (0x0100) #define NS9750_MEM_DYN_RAS_CAS_BASE (0x0104) @@ -102,7 +102,7 @@ #define NS9750_MEM_DYN_REFRESH_MA (0x000007FF) #define NS9750_MEM_DYN_READ_CFG_MA (0x00000003) -#define NS9750_MEM_DYN_READ_CFG_DELAY0 (0x00000001) +#define NS9750_MEM_DYN_READ_CFG_DELAY0 (0x00000001) #define NS9750_MEM_DYN_READ_CFG_DELAY1 (0x00000002) #define NS9750_MEM_DYN_READ_CFG_DELAY2 (0x00000003) @@ -137,13 +137,13 @@ #define NS9750_MEM_DYN_CFG_MD (0x00000018) #define NS9750_MEM_DYN_RAS_CAS_CAS_MA (0x00000300) -#define NS9750_MEM_DYN_RAS_CAS_CAS_1 (0x00000100) -#define NS9750_MEM_DYN_RAS_CAS_CAS_2 (0x00000200) -#define NS9750_MEM_DYN_RAS_CAS_CAS_3 (0x00000300) +#define NS9750_MEM_DYN_RAS_CAS_CAS_1 (0x00000100) +#define NS9750_MEM_DYN_RAS_CAS_CAS_2 (0x00000200) +#define NS9750_MEM_DYN_RAS_CAS_CAS_3 (0x00000300) #define NS9750_MEM_DYN_RAS_CAS_RAS_MA (0x00000003) #define NS9750_MEM_DYN_RAS_CAS_RAS_1 (0x00000001) -#define NS9750_MEM_DYN_RAS_CAS_RAS_2 (0x00000002) -#define NS9750_MEM_DYN_RAS_CAS_RAS_3 (0x00000003) +#define NS9750_MEM_DYN_RAS_CAS_RAS_2 (0x00000002) +#define NS9750_MEM_DYN_RAS_CAS_RAS_3 (0x00000003) #define NS9750_MEM_STAT_CFG_PSMC (0x00100000) #define NS9750_MEM_STAT_CFG_BSMC (0x00080000) @@ -153,7 +153,7 @@ #define NS9750_MEM_STAT_CFG_PM (0x00000008) #define NS9750_MEM_STAT_CFG_MW_MA (0x00000003) #define NS9750_MEM_STAT_CFG_MW_8 (0x00000000) -#define NS9750_MEM_STAT_CFG_MW_16 (0x00000001) +#define NS9750_MEM_STAT_CFG_MW_16 (0x00000001) #define NS9750_MEM_STAT_CFG_MW_32 (0x00000002) #define NS9750_MEM_STAT_WAIT_WEN_MA (0x0000000F) |