Rename common ns16550 constants with UART_ prefix to prevent conflicts

Fix problems introduced in commit
7b5611cdd12ca0cc33f994f0d4a4454788fc3124 [inka4x0: Add hardware
diagnosis functions for inka4x0] which redefined MSR_RI which is
already used on PowerPC systems.

Also eliminate redundant definitions in ps2mult.h.  More cleanup will
be needed for other redundant occurrences though.

Signed-off-by: Detlev Zundel <dzu@denx.de>

1 files changed, 93 insertions, 42 deletions

diff --git a/include/ns16550.h b/include/ns16550.h
index edfbc53..87624bf 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -1,6 +1,10 @@
 /*
  * NS16550 Serial Port
  * originally from linux source (arch/ppc/boot/ns16550.h)
+ *
+ * Cleanup and unification
+ * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
+ *
  * modified slightly to
  * have addresses as offsets from CONFIG_SYS_ISA_BASE
  * added a few more definitions
@@ -115,53 +119,100 @@ struct NS16550 {
 
 typedef volatile struct NS16550 *NS16550_t;
 
-#define FCR_FIFO_EN     0x01		/* Fifo enable */
-#define FCR_RXSR        0x02		/* Receiver soft reset */
-#define FCR_TXSR        0x04		/* Transmitter soft reset */
-
-#define MCR_DTR         0x01
-#define MCR_RTS         0x02
-#define MCR_DMA_EN      0x04
-#define MCR_TX_DFR      0x08
-#define MCR_LOOP	0x10		/* Enable loopback test mode */
-
-#define LCR_WLS_MSK	0x03		/* character length select mask */
-#define LCR_WLS_5	0x00		/* 5 bit character length */
-#define LCR_WLS_6	0x01		/* 6 bit character length */
-#define LCR_WLS_7	0x02		/* 7 bit character length */
-#define LCR_WLS_8	0x03		/* 8 bit character length */
-#define LCR_STB		0x04		/* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN		0x08		/* Parity eneble */
-#define LCR_EPS		0x10		/* Even Parity Select */
-#define LCR_STKP	0x20		/* Stick Parity */
-#define LCR_SBRK	0x40		/* Set Break */
-#define LCR_BKSE	0x80		/* Bank select enable */
-#define LCR_DLAB	0x80		/* Divisor latch access bit */
-
-#define LSR_DR		0x01		/* Data ready */
-#define LSR_OE		0x02		/* Overrun */
-#define LSR_PE		0x04		/* Parity error */
-#define LSR_FE		0x08		/* Framing error */
-#define LSR_BI		0x10		/* Break */
-#define LSR_THRE	0x20		/* Xmit holding register empty */
-#define LSR_TEMT	0x40		/* Xmitter empty */
-#define LSR_ERR		0x80		/* Error */
-
-#define MSR_DCD		0x80		/* Data Carrier Detect */
-#define MSR_RI		0x40		/* Ring Indicator */
-#define MSR_DSR		0x20		/* Data Set Ready */
-#define MSR_CTS		0x10		/* Clear to Send */
-#define MSR_DDCD	0x08		/* Delta DCD */
-#define MSR_TERI	0x04		/* Trailing edge ring indicator */
-#define MSR_DDSR	0x02		/* Delta DSR */
-#define MSR_DCTS	0x01		/* Delta CTS */
+/*
+ * These are the definitions for the FIFO Control Register
+ */
+#define UART_FCR_FIFO_EN 	0x01 /* Fifo enable */
+#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
+
+#define UART_FCR_RXSR		0x02 /* Receiver soft reset */
+#define UART_FCR_TXSR		0x04 /* Transmitter soft reset */
+
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_DTR	0x01		/* DTR   */
+#define UART_MCR_RTS	0x02		/* RTS   */
+#define UART_MCR_OUT1	0x04		/* Out 1 */
+#define UART_MCR_OUT2	0x08		/* Out 2 */
+#define UART_MCR_LOOP	0x10		/* Enable loopback test mode */
+
+#define UART_MCR_DMA_EN	0x04
+#define UART_MCR_TX_DFR	0x08
+
+/*
+ * These are the definitions for the Line Control Register
+ *
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define UART_LCR_WLS_MSK 0x03		/* character length select mask */
+#define UART_LCR_WLS_5	0x00		/* 5 bit character length */
+#define UART_LCR_WLS_6	0x01		/* 6 bit character length */
+#define UART_LCR_WLS_7	0x02		/* 7 bit character length */
+#define UART_LCR_WLS_8	0x03		/* 8 bit character length */
+#define UART_LCR_STB	0x04		/* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define UART_LCR_PEN	0x08		/* Parity eneble */
+#define UART_LCR_EPS	0x10		/* Even Parity Select */
+#define UART_LCR_STKP	0x20		/* Stick Parity */
+#define UART_LCR_SBRK	0x40		/* Set Break */
+#define UART_LCR_BKSE	0x80		/* Bank select enable */
+#define UART_LCR_DLAB	0x80		/* Divisor latch access bit */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_DR	0x01		/* Data ready */
+#define UART_LSR_OE	0x02		/* Overrun */
+#define UART_LSR_PE	0x04		/* Parity error */
+#define UART_LSR_FE	0x08		/* Framing error */
+#define UART_LSR_BI	0x10		/* Break */
+#define UART_LSR_THRE	0x20		/* Xmit holding register empty */
+#define UART_LSR_TEMT	0x40		/* Xmitter empty */
+#define UART_LSR_ERR	0x80		/* Error */
+
+#define UART_MSR_DCD	0x80		/* Data Carrier Detect */
+#define UART_MSR_RI	0x40		/* Ring Indicator */
+#define UART_MSR_DSR	0x20		/* Data Set Ready */
+#define UART_MSR_CTS	0x10		/* Clear to Send */
+#define UART_MSR_DDCD	0x08		/* Delta DCD */
+#define UART_MSR_TERI	0x04		/* Trailing edge ring indicator */
+#define UART_MSR_DDSR	0x02		/* Delta DSR */
+#define UART_MSR_DCTS	0x01		/* Delta CTS */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
+#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
+
+#define UART_IIR_MSI	0x00	/* Modem status interrupt */
+#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
+#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
+#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
+#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
+#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
+#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
+
 
 #ifdef CONFIG_OMAP1510
-#define OSC_12M_SEL	0x01		/* selects 6.5 * current clk div */
+#define OSC_12M_SEL	0x01	/* selects 6.5 * current clk div */
 #endif
 
 /* useful defaults for LCR */
-#define LCR_8N1		0x03
+#define UART_LCR_8N1	0x03
 
 void	NS16550_init   (NS16550_t com_port, int baud_divisor);
 void	NS16550_putc   (NS16550_t com_port, char c);