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| author | Stefan Roese <sr@denx.de> | 2007-07-04 08:11:37 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-07-04 08:11:37 +0200 |
| commit | 8e990cb076a1c77daf3a50cc0df9732135e9eef5 (patch) | |
| tree | 3b860d74bb4ddc5e0c9485e44da1bc0a08ed839c /include/mpc8xx.h | |
| parent | d677b32855f577ae2690dcd64a172cdd706e0ffc (diff) | |
| parent | 98c440bee623ecdd5322852732b883e696fb2140 (diff) | |
| download | u-boot-imx-8e990cb076a1c77daf3a50cc0df9732135e9eef5.zip u-boot-imx-8e990cb076a1c77daf3a50cc0df9732135e9eef5.tar.gz u-boot-imx-8e990cb076a1c77daf3a50cc0df9732135e9eef5.tar.bz2 | |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'include/mpc8xx.h')
| -rw-r--r-- | include/mpc8xx.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/include/mpc8xx.h b/include/mpc8xx.h index 2911758..bef748f 100644 --- a/include/mpc8xx.h +++ b/include/mpc8xx.h @@ -35,7 +35,7 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ - +#define _START_OFFSET EXC_OFF_SYS_RESET /*----------------------------------------------------------------------- * SYPCR - System Protection Control Register 11-9 @@ -208,12 +208,12 @@ #define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */ #define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */ #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ -#define SCCR_DFNL001 0x00000100 /* Division by 4 */ -#define SCCR_DFNL010 0x00000200 /* Division by 8 */ -#define SCCR_DFNL011 0x00000300 /* Division by 16 */ -#define SCCR_DFNL100 0x00000400 /* Division by 32 */ -#define SCCR_DFNL101 0x00000500 /* Division by 64 */ -#define SCCR_DFNL110 0x00000600 /* Division by 128 */ +#define SCCR_DFNL001 0x00000100 /* Division by 4 */ +#define SCCR_DFNL010 0x00000200 /* Division by 8 */ +#define SCCR_DFNL011 0x00000300 /* Division by 16 */ +#define SCCR_DFNL100 0x00000400 /* Division by 32 */ +#define SCCR_DFNL101 0x00000500 /* Division by 64 */ +#define SCCR_DFNL110 0x00000600 /* Division by 128 */ #define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */ #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ #define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */ |