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| author | Anton Vorontsov <avorontsov@ru.mvista.com> | 2008-05-29 18:14:56 +0400 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-06-10 18:22:25 -0500 |
| commit | c8c5fc266e4499e283c293ccb972863156aa4134 (patch) | |
| tree | 1a5c26b92c3c663d672fe89127b18a566d382712 /include/mpc85xx.h | |
| parent | 42dbd667c88d496882d53e22656e89b654205492 (diff) | |
| download | u-boot-imx-c8c5fc266e4499e283c293ccb972863156aa4134.zip u-boot-imx-c8c5fc266e4499e283c293ccb972863156aa4134.tar.gz u-boot-imx-c8c5fc266e4499e283c293ccb972863156aa4134.tar.bz2 | |
83xx/85xx: further localbus cleanups
Merge mpc85xx.h's LBC defines to fsl_lbc.h. Also, adopt ACS names
from mpc85xx.h, so ACS_0b10 renamed to ACS_DIV4, ACS_0b11 to ACS_DIV2.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Diffstat (limited to 'include/mpc85xx.h')
| -rw-r--r-- | include/mpc85xx.h | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/include/mpc85xx.h b/include/mpc85xx.h index da323e8..a4d4d65 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -28,39 +28,4 @@ #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ -/* - * Local Bus Controller - memory controller registers - */ -#define BRx_V 0x00000001 /* Bank Valid */ -#define BRx_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ -#define BRx_MS_SDRAM 0x00000000 /* SDRAM Machine Select */ -#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ -#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */ -#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */ -#define BRx_PS_8 0x00000800 /* 8 bit port size */ -#define BRx_PS_32 0x00001800 /* 32 bit port size */ -#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */ - -#define ORxG_EAD 0x00000001 /* External addr latch delay */ -#define ORxG_EHTR 0x00000002 /* Extended hold time on read */ -#define ORxG_TRLX 0x00000004 /* Timing relaxed */ -#define ORxG_SETA 0x00000008 /* External address termination */ -#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ -#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ -#define ORxG_XACS 0x00000100 /* Extra addr to CS setup */ -#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/ -#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */ - -#define ORxU_BI 0x00000100 /* Burst Inhibit */ -#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */ - -#define MxMR_OP_NORM 0x00000000 /* Normal Operation */ -#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ -#define MxMR_OP_WARR 0x10000000 /* Write to Array */ -#define MxMR_BSEL 0x80000000 /* Bus Select */ - -/* helpers to convert values into an OR address mask (GPCM mode) */ -#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ -#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20) - #endif /* __MPC85xx_H__ */ |