diff options
| author | John Rigby <jrigby@freescale.com> | 2007-07-10 14:58:41 -0600 |
|---|---|---|
| committer | John Rigby <jrigby@freescale.com> | 2007-07-10 14:58:41 -0600 |
| commit | 98c80b462f9532f3ff6a62dd9629023b48627a6d (patch) | |
| tree | bea13c7b7f892aa5875e737bd52535be50d96d25 /include/mpc83xx.h | |
| parent | 0dca874db62718e41253659e60f3a1de7eb418ce (diff) | |
| parent | 4ef218f6fdf8d747f4589da5252b004e7d2c2876 (diff) | |
| download | u-boot-imx-98c80b462f9532f3ff6a62dd9629023b48627a6d.zip u-boot-imx-98c80b462f9532f3ff6a62dd9629023b48627a6d.tar.gz u-boot-imx-98c80b462f9532f3ff6a62dd9629023b48627a6d.tar.bz2 | |
Merge branch 'master' into u-boot-5329-early
Diffstat (limited to 'include/mpc83xx.h')
| -rw-r--r-- | include/mpc83xx.h | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 60fc214..336c0ac 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -25,6 +25,7 @@ /* System reset offset (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET /* IMMRBAR - Internal Memory Register Base Address */ @@ -438,9 +439,9 @@ #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 #if defined(CONFIG_MPC831X) -#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 +#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 -#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 +#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 #define HRCWH_RL_EXT_LEGACY 0x00000000 @@ -1217,7 +1218,7 @@ #define FCR_CMD1 0x00FF0000 #define FCR_CMD1_SHIFT 16 #define FCR_CMD2 0x0000FF00 -#define FCR_CMD2_SHIFT 8 +#define FCR_CMD2_SHIFT 8 #define FCR_CMD3 0x000000FF #define FCR_CMD3_SHIFT 0 @@ -1241,8 +1242,8 @@ /* LTESR - Transfer Error Status Register */ #define LTESR_BM 0x80000000 -#define LTESR_FCT 0x40000000 -#define LTESR_PAR 0x20000000 +#define LTESR_FCT 0x40000000 +#define LTESR_PAR 0x20000000 #define LTESR_WP 0x04000000 #define LTESR_ATMW 0x00800000 #define LTESR_ATMR 0x00400000 |