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authorStefan Roese <sr@denx.de>2007-08-21 16:33:33 +0200
committerStefan Roese <sr@denx.de>2007-08-21 16:33:33 +0200
commit93f798346033a1f6d22090b47abad4be88243b04 (patch)
tree45b4d2a887a89572015de3234b04b419bfc11b44 /include/mpc83xx.h
parent3ad63878737a5a2b1e60825bf0a7d601d7a695e7 (diff)
parent3e66c078003607a7d1d214c15a5f262bc1b4032f (diff)
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Merge with /home/stefan/git/u-boot/u-boot-ppc4xx
Diffstat (limited to 'include/mpc83xx.h')
-rw-r--r--include/mpc83xx.h9
1 files changed, 7 insertions, 2 deletions
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 336c0ac..4d32c6a 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -86,6 +86,8 @@
#define SPR_8360_REV12 0x80490012
#define SPR_8360E_REV20 0x80480020
#define SPR_8360_REV20 0x80490020
+#define SPR_8360E_REV21 0x80480021
+#define SPR_8360_REV21 0x80490021
#define SPR_8323E_REV10 0x80620010
#define SPR_8323_REV10 0x80630010
@@ -600,7 +602,9 @@
#define SCCR_TSEC1CM_3 0xC0000000
#define SCCR_TSEC1ON 0x20000000
+#define SCCR_TSEC1ON_SHIFT 29
#define SCCR_TSEC2ON 0x10000000
+#define SCCR_TSEC2ON_SHIFT 28
#endif
@@ -701,8 +705,9 @@
#define SDRAM_CFG_SREN 0x40000000
#define SDRAM_CFG_ECC_EN 0x20000000
#define SDRAM_CFG_RD_EN 0x10000000
-#define SDRAM_CFG_SDRAM_TYPE 0x03000000
-#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#define SDRAM_CFG_32_BE 0x00080000