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authorDave Liu <daveliu@freescale.com>2006-10-25 14:41:21 -0500
committerKim Phillips <kim.phillips@freescale.com>2006-11-03 19:42:18 -0600
commitf6eda7f80ccc13d658020268c507d7173cf2e8aa (patch)
treeeb9ddcc13eab92630486bd7da53258c7cd704086 /include/mpc83xx.h
parent3894c46c27c64891f93ac04edde86a9fa9758d92 (diff)
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mpc83xx: Changed to unified mpx83xx names and added common 83xx changes
Incorporated the common unified variable names and the changes in preparation for releasing mpc8360 patches. Signed-off-by: Dave Liu <daveliu@freescale.com>
Diffstat (limited to 'include/mpc83xx.h')
-rw-r--r--include/mpc83xx.h40
1 files changed, 39 insertions, 1 deletions
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index ea40bad3..d5b7bca 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2004 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -29,6 +29,7 @@
#ifndef __MPC83XX_H__
#define __MPC83XX_H__
+#include <config.h>
#if defined(CONFIG_E300)
#include <asm/e300.h>
#endif
@@ -85,6 +86,11 @@
#define LBLAWBAR3 0x0038
#define LBLAWAR3 0x003C
+/*
+ * The device ID and revision numbers
+ */
+#define SPR_8349E_REV10 0x80300100
+#define SPR_8349E_REV11 0x80300101
/*
* Base Registers & Option Registers
@@ -243,6 +249,12 @@
#define HRCWH_BIG_ENDIAN 0x00000000
#define HRCWH_LITTLE_ENDIAN 0x00000008
+#define HRCWH_LALE_NORMAL 0x00000000
+#define HRCWH_LALE_EARLY 0x00000004
+
+#define HRCWH_LDP_SET 0x00000000
+#define HRCWH_LDP_CLEAR 0x00000002
+
/*
* Hard Reset Configration Word - Low
*/
@@ -310,4 +322,30 @@
#define LCRR_CLKDIV_8 0x00000008
#define LCRR_CLKDIV_SHIFT 0
+/*
+ * SCCR-System Clock Control Register
+ */
+#define SCCR_TSEC1CM_0 0x00000000
+#define SCCR_TSEC1CM_1 0x40000000
+#define SCCR_TSEC1CM_2 0x80000000
+#define SCCR_TSEC1CM_3 0xC0000000
+#define SCCR_TSEC2CM_0 0x00000000
+#define SCCR_TSEC2CM_1 0x10000000
+#define SCCR_TSEC2CM_2 0x20000000
+#define SCCR_TSEC2CM_3 0x30000000
+#define SCCR_ENCCM_0 0x00000000
+#define SCCR_ENCCM_1 0x01000000
+#define SCCR_ENCCM_2 0x02000000
+#define SCCR_ENCCM_3 0x03000000
+#define SCCR_USBCM_0 0x00000000
+#define SCCR_USBCM_1 0x00500000
+#define SCCR_USBCM_2 0x00A00000
+#define SCCR_USBCM_3 0x00F00000
+
+#define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \
+ | SCCR_TSEC2CM_3 \
+ | SCCR_ENCCM_3 \
+ | SCCR_USBCM_3 )
+#define SCCR_DEFAULT 0xFFFFFFFF
+
#endif /* __MPC83XX_H__ */