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| author | Stefan Roese <sr@denx.de> | 2008-01-17 16:04:12 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-01-17 16:04:12 +0100 |
| commit | 9cfff9e9d4d9dbb9bb428cea3fa2cda3b3e593ad (patch) | |
| tree | 7e3e5036eef33672f6c40c5f6aca68f34f5b3a31 /include/mpc83xx.h | |
| parent | 3259eeaa4148125a81417477f62c05bd67f60587 (diff) | |
| parent | 4c9e98ace78e7de972adf7da7135a46ec0a4ee7e (diff) | |
| download | u-boot-imx-9cfff9e9d4d9dbb9bb428cea3fa2cda3b3e593ad.zip u-boot-imx-9cfff9e9d4d9dbb9bb428cea3fa2cda3b3e593ad.tar.gz u-boot-imx-9cfff9e9d4d9dbb9bb428cea3fa2cda3b3e593ad.tar.bz2 | |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'include/mpc83xx.h')
| -rw-r--r-- | include/mpc83xx.h | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 7299ca0..39cecf2 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -725,13 +725,20 @@ #define SCCR_USBCM_3 0x00F00000 #elif defined(CONFIG_MPC8313) -/* TSEC1 bits are for TSEC2 as well */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 +#define SCCR_TSEC1CM_0 0x00000000 #define SCCR_TSEC1CM_1 0x40000000 #define SCCR_TSEC1CM_2 0x80000000 #define SCCR_TSEC1CM_3 0xC0000000 +#define SCCR_TSEC2CM 0x30000000 +#define SCCR_TSEC2CM_SHIFT 28 +#define SCCR_TSEC2CM_0 0x00000000 +#define SCCR_TSEC2CM_1 0x10000000 +#define SCCR_TSEC2CM_2 0x20000000 +#define SCCR_TSEC2CM_3 0x30000000 + #define SCCR_TSEC1ON 0x20000000 #define SCCR_TSEC1ON_SHIFT 29 #define SCCR_TSEC2ON 0x10000000 @@ -831,8 +838,6 @@ #define SCCR_PCIEXP2CM_3 0x000c0000 /* All of the four SATA controllers must have the same clock ratio */ -#define SCCR_SATA1CM 0x000000c0 -#define SCCR_SATA1CM_SHIFT 6 #define SCCR_SATACM 0x000000ff #define SCCR_SATACM_SHIFT 0 #define SCCR_SATACM_0 0x00000000 @@ -852,6 +857,7 @@ */ #define CSCONFIG_EN 0x80000000 #define CSCONFIG_AP 0x00800000 +#define CSCONFIG_ODT_WR_ACS 0x00010000 #define CSCONFIG_ROW_BIT 0x00000700 #define CSCONFIG_ROW_BIT_12 0x00000000 #define CSCONFIG_ROW_BIT_13 0x00000100 @@ -1480,6 +1486,7 @@ /* DDRCDR - DDR Control Driver Register */ +#define DDRCDR_DHC_EN 0x80000000 #define DDRCDR_EN 0x40000000 #define DDRCDR_PZ 0x3C000000 #define DDRCDR_PZ_MAXZ 0x00000000 |