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| author | Xie Xiaobo <r63061@freescale.com> | 2007-02-14 18:26:44 +0800 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2007-03-02 11:05:54 -0600 |
| commit | 8d172c0f0d85998a256a95b7459a5403a30380ed (patch) | |
| tree | 5b9e523bd934cb6e96131a1fae190d9156f294ad /include/mpc83xx.h | |
| parent | f6f5f709e5c8e4564c4dfeecfdf2279244f9c83b (diff) | |
| download | u-boot-imx-8d172c0f0d85998a256a95b7459a5403a30380ed.zip u-boot-imx-8d172c0f0d85998a256a95b7459a5403a30380ed.tar.gz u-boot-imx-8d172c0f0d85998a256a95b7459a5403a30380ed.tar.bz2 | |
mpc83xx: Add the cpu and board specific code for MPC8349E rev3.1 MDS
MPC8349E rev3.1 have new spridr,and PVR value,
The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM.
Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>
Diffstat (limited to 'include/mpc83xx.h')
| -rw-r--r-- | include/mpc83xx.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 1b62f81..73f2721 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -68,6 +68,15 @@ #define SPR_8343E_REV11 0x80360101 #define SPR_8343_REV11 0x80370101 +#define SPR_8349E_REV31 0x80300300 +#define SPR_8349_REV31 0x80310300 +#define SPR_8347E_REV31_TBGA 0x80320300 +#define SPR_8347_REV31_TBGA 0x80330300 +#define SPR_8347E_REV31_PBGA 0x80340300 +#define SPR_8347_REV31_PBGA 0x80350300 +#define SPR_8343E_REV31 0x80360300 +#define SPR_8343_REV31 0x80370300 + #define SPR_8360E_REV10 0x80480010 #define SPR_8360_REV10 0x80490010 #define SPR_8360E_REV11 0x80480011 @@ -573,8 +582,8 @@ /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */ -#define TIMING_CFG2_CPO 0x0F000000 -#define TIMING_CFG2_CPO_SHIFT 24 +#define TIMING_CFG2_CPO 0x0F800000 +#define TIMING_CFG2_CPO_SHIFT 23 #define TIMING_CFG2_ACSM 0x00080000 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 |