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authorMichal Simek <monstr@monstr.eu>2007-07-13 21:39:13 +0200
committerMichal Simek <monstr@monstr.eu>2007-07-13 21:39:13 +0200
commitbc2962482b707e44e0b43d20bd4dcf2a40230abb (patch)
tree751c5e07c5ff0aa7910da0fe33b0a0996bda518c /include/mpc8260.h
parent093172f08d6afb3f34d8a2f26ee0ee874261cf27 (diff)
parent239f05ee4dd4cfe0b50f251b533dcebe9e67c360 (diff)
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Merge git://www.denx.de/git/u-boot
Diffstat (limited to 'include/mpc8260.h')
-rw-r--r--include/mpc8260.h18
1 files changed, 9 insertions, 9 deletions
diff --git a/include/mpc8260.h b/include/mpc8260.h
index d9dd92d..0525294 100644
--- a/include/mpc8260.h
+++ b/include/mpc8260.h
@@ -53,7 +53,7 @@
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
-
+#define _START_OFFSET EXC_OFF_SYS_RESET
/*-----------------------------------------------------------------------
* BCR - Bus Configuration Register 4-25
@@ -664,7 +664,7 @@
#define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */
/*-----------------------------------------------------------------------
- * LSDMR - Local Bus SDRAM Mode Register 10-24
+ * LSDMR - Local Bus SDRAM Mode Register 10-24
*/
/*
@@ -707,23 +707,23 @@
/*-----------------------------------------------------------------------
* TMR1-TMR4 - Timer Mode Registers 17-6
*/
-#define TMRx_PS_MSK 0xff00 /* Prescaler Value */
+#define TMRx_PS_MSK 0xff00 /* Prescaler Value */
#define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/
-#define TMRx_OM 0x0020 /* Output Mode */
+#define TMRx_OM 0x0020 /* Output Mode */
#define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/
-#define TMRx_FRR 0x0008 /* Free Run/Restart */
+#define TMRx_FRR 0x0008 /* Free Run/Restart */
#define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
-#define TMRx_GE 0x0001 /* Gate Enable */
+#define TMRx_GE 0x0001 /* Gate Enable */
#define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/
#define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
#define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
-#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */
+#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */
-#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
+#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
#define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/
#define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/
-#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */
+#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */
/*-----------------------------------------------------------------------