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| author | wdenk <wdenk> | 2003-08-05 18:22:44 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-08-05 18:22:44 +0000 |
| commit | 96e48cf6c14319f87b38a1d3b6ec9139c9d0469d (patch) | |
| tree | 7e9f40e0a4bc9dcdda65bf7018ebc9f315df8bee /include/mpc5xxx.h | |
| parent | bdccc4fedcf9c5fc1f06e8f833d792198c9d04ae (diff) | |
| download | u-boot-imx-96e48cf6c14319f87b38a1d3b6ec9139c9d0469d.zip u-boot-imx-96e48cf6c14319f87b38a1d3b6ec9139c9d0469d.tar.gz u-boot-imx-96e48cf6c14319f87b38a1d3b6ec9139c9d0469d.tar.bz2 | |
* Fix PCI support for MPC5200 / IceCube Board
Diffstat (limited to 'include/mpc5xxx.h')
| -rw-r--r-- | include/mpc5xxx.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index e0f2367..b803d03 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -61,6 +61,10 @@ #if defined(CONFIG_MGT5100) #define MPC5XXX_SDRAM_START (CFG_MBAR + 0x0034) #define MPC5XXX_SDRAM_STOP (CFG_MBAR + 0x0038) +#define MPC5XXX_PCI1_START (CFG_MBAR + 0x003c) +#define MPC5XXX_PCI1_STOP (CFG_MBAR + 0x0040) +#define MPC5XXX_PCI2_START (CFG_MBAR + 0x0044) +#define MPC5XXX_PCI2_STOP (CFG_MBAR + 0x0048) #elif defined(CONFIG_MPC5200) #define MPC5XXX_CS6_START (CFG_MBAR + 0x0058) #define MPC5XXX_CS6_STOP (CFG_MBAR + 0x005c) @@ -75,6 +79,7 @@ #define MPC5XXX_LPB (CFG_MBAR + 0x0300) #define MPC5XXX_ICTL (CFG_MBAR + 0x0500) #define MPC5XXX_GPIO (CFG_MBAR + 0x0b00) +#define MPC5XXX_PCI (CFG_MBAR + 0x0d00) #define MPC5XXX_SDMA (CFG_MBAR + 0x1200) #define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00) @@ -136,6 +141,33 @@ /* GPIO registers */ #define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000) +/* PCI registers */ +#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04) +#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c) +#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10) +#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14) +#if defined(CONFIG_MGT5100) +#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68) +#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c) +#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70) +#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74) +#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78) +#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c) +#elif defined(CONFIG_MPC5200) +#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60) +#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64) +#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68) +#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c) +#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70) +#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74) +#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78) +#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80) +#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84) +#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88) +#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c) +#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8) +#endif + /* Interrupt Controller registers */ #define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000) #define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004) |