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author | Rafal Jaworowski <raj@pollux.denx.de> | 2006-03-29 13:17:09 +0200 |
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committer | Rafal Jaworowski <raj@pollux.denx.de> | 2006-03-29 13:17:09 +0200 |
commit | b66a9383421805c705654ce9456ec28c202819fb (patch) | |
tree | 4fb429d1b2402185225d8aed5fa551afff9b507a /include/mpc5xxx.h | |
parent | 7b4fd36b0322ec98836a8459d9be80e2777fdc05 (diff) | |
download | u-boot-imx-b66a9383421805c705654ce9456ec28c202819fb.zip u-boot-imx-b66a9383421805c705654ce9456ec28c202819fb.tar.gz u-boot-imx-b66a9383421805c705654ce9456ec28c202819fb.tar.bz2 |
Set SDelay register in the DDR controller for the MPC5200B chip.
Diffstat (limited to 'include/mpc5xxx.h')
-rw-r--r-- | include/mpc5xxx.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index f33d858..50a6ac1 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -131,6 +131,7 @@ #if defined(CONFIG_MGT5100) #define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010) #endif +#define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090) /* Clock Distribution Module */ #define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000) |