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authorwdenk <wdenk>2003-08-28 09:41:22 +0000
committerwdenk <wdenk>2003-08-28 09:41:22 +0000
commitd94f92cbd7f4a4d3bf0d5d963b709c686e8f6633 (patch)
treec85dd4a10c5a68ca09b9139c1b6428d55ada6451 /include/mpc5xxx.h
parente0ac62d798ce60ec5d43125d4786e58b0d881836 (diff)
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* Fix ICU862 environment problem
* Fix RAM size detection for RMU board * Implement "reset" for MGT5100/MPC5200 systems
Diffstat (limited to 'include/mpc5xxx.h')
-rw-r--r--include/mpc5xxx.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index b803d03..4218b05 100644
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -78,6 +78,7 @@
#define MPC5XXX_CDM (CFG_MBAR + 0x0200)
#define MPC5XXX_LPB (CFG_MBAR + 0x0300)
#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
+#define MPC5XXX_GPT (CFG_MBAR + 0x0600)
#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
@@ -183,6 +184,10 @@
#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
+/* General Purpose Timers registers */
+#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
+#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
+
/* Programmable Serial Controller (PSC) status register bits */
#define PSC_SR_CDE 0x0080
#define PSC_SR_RXRDY 0x0100