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author | Daniel Hellstrom <daniel@gaisler.com> | 2008-03-28 20:40:19 +0100 |
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committer | Stefan Roese <sr@denx.de> | 2008-03-29 06:51:04 +0100 |
commit | 97bf85d784fbed485e652eb907589ad0d5cb7262 (patch) | |
tree | bfff8d652628f9363f275702b85a37317973baa1 /include/lh7a404.h | |
parent | 90447ecbbac8572457b6d8903073ac3f120995ba (diff) | |
download | u-boot-imx-97bf85d784fbed485e652eb907589ad0d5cb7262.zip u-boot-imx-97bf85d784fbed485e652eb907589ad0d5cb7262.tar.gz u-boot-imx-97bf85d784fbed485e652eb907589ad0d5cb7262.tar.bz2 |
MTD/CFI: flash_read64 is defined a weak function (for SPARC)
SPARC has implemented __raw_readq, it reads 64-bit from any 32-bit address.
SPARC CPUs implement flash_read64 which calls __raw_readq.
For current SPARC architectures (LEON2 and LEON3) each read from the
FLASH must lead to a cache miss. This is because FLASH can not be set
non-cacheable since program code resides there, and alternatively disabling
cache is poor from performance view, or doing a cache flush between each
read is even poorer.
Forcing a cache miss on a SPARC is done by a special instruction "lda" -
load alternative space, the alternative space number (ASI) is processor
implementation spcific and can be found by including <asm/processor.h>.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
Diffstat (limited to 'include/lh7a404.h')
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