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| author | Lily Zhang <r58066@freescale.com> | 2011-09-23 20:36:23 +0800 |
|---|---|---|
| committer | Lily Zhang <r58066@freescale.com> | 2011-09-23 21:04:43 +0800 |
| commit | aae7b1d7215fc2cc5c5ecc9f1ace637cff56425f (patch) | |
| tree | 351efa2a65387197957b87e765c5db1c6e91968a /include/jffs2 | |
| parent | 0ff764f10e14df31e80cb4d6cc3766e8e7813384 (diff) | |
| download | u-boot-imx-aae7b1d7215fc2cc5c5ecc9f1ace637cff56425f.zip u-boot-imx-aae7b1d7215fc2cc5c5ecc9f1ace637cff56425f.tar.gz u-boot-imx-aae7b1d7215fc2cc5c5ecc9f1ace637cff56425f.tar.bz2 | |
ENGR00157538 remove VDIG_PLL setting in plug-in code
According to the datasheet, VDIG_PLL needs to be increased
to 1.3v for TO2.0. This operation has been done in the
low_level_init.S. Remove the duplicated code here.
Signed-off-by: Lily Zhang <r58066@freescale.com>
Diffstat (limited to 'include/jffs2')
0 files changed, 0 insertions, 0 deletions