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| author | York Sun <yorksun@freescale.com> | 2012-08-17 08:22:42 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-08-23 12:16:56 -0500 |
| commit | 62f739fe465c41a2c5be0a46b3330c12b213dc07 (patch) | |
| tree | 84d1764a5c706e3618b10b999781eab6e3b02142 /include/ipu_pixfmt.h | |
| parent | 7e4db27ffd11f3eea7e4dfc33354fd087f9257d8 (diff) | |
| download | u-boot-imx-62f739fe465c41a2c5be0a46b3330c12b213dc07.zip u-boot-imx-62f739fe465c41a2c5be0a46b3330c12b213dc07.tar.gz u-boot-imx-62f739fe465c41a2c5be0a46b3330c12b213dc07.tar.bz2 | |
powerpc/mpc8xxx DDR: Fall back to raw timing for first controller only
Only the first DIMM of first controller should fall back to raw timing
parameters if SPD is missing or corrupted.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include/ipu_pixfmt.h')
0 files changed, 0 insertions, 0 deletions