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authorAnish Trivedi <anish@freescale.com>2011-06-22 17:49:45 -0500
committerAnish Trivedi <anish@freescale.com>2011-07-05 14:28:09 -0500
commit82102d3fdeae0dcd79d9b3ab7daa96bebd5ad290 (patch)
treea21029195468b8d1ffcc134d8bb25fb6e724eb90 /include/fsl_esdhc.h
parentc2ee955784881a2f3ac4c0cc234ba23d83205cb1 (diff)
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ENGR00139206 MX6 USDHC eMMC 4.4 support
New bit definitions in USDHC. Added is_usdhc variable to fsl_esdhc_cfg to distinguish between ESDHC and USDHC. Enabled DDR mode support in USDHC. Created a config to customize target delay for DDR mode. Modified USDHC pad settings to make DDR mode work for all emmcs at 50 MHz. Signed-off-by: Anish Trivedi <anish@freescale.com>
Diffstat (limited to 'include/fsl_esdhc.h')
-rw-r--r--include/fsl_esdhc.h16
1 files changed, 12 insertions, 4 deletions
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 08e62a5..fe62c01 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -151,10 +151,8 @@
#define ESDHC_HOSTVER_VVN_MASK 0x0000ff00
#define ESDHC_HOSTVER_VVN_SHIFT 8
-#define ESDHC_HOSTVER_DDR_SUPPORT 0x13
-#define USDHC_HOSTVER_VVN 0x0
-
-#define SDHC_IS_USDHC(x) (x == USDHC_HOSTVER_VVN)
+#define ESDHC_HOSTVER_SVN_MASK 0x000000ff
+#define ESDHC_HOSTVER_SVN_SHIFT 0
#define ESDHC_DLLCTRL_SLV_OVERRIDE_VAL 12
#define ESDHC_DLLCTRL_SLV_OVERRIDE_VAL_MASK 0x0000FC00
@@ -165,10 +163,20 @@
#define ESDHC_DLL_TARGET_DEFAULT_VAL 4
#define ESDHC_DLLSTS_SLV_LOCK_MASK 0x00000001
+#define USDHC_DLLCTRL_SLV_OVERRIDE_VAL_MASK 0x0000FE00
+#define USDHC_DLLCTRL_SLV_OVERRIDE_VAL_SHIFT 9
+#define USDHC_DLLCTRL_SLV_OVERRIDE 0x100
+#define USDHC_DLLCTRL_TARGET_MASK 0x00070078
+#define USDHC_DLLCTRL_TARGET_LOW_SHIFT 3
+#define USDHC_DLLCTRL_TARGET_HIGH_SHIFT 16
+#define USDHC_DLL_LOW_MASK 0xF
+#define USDHC_DLL_HIGH_SHIFT 4
+
struct fsl_esdhc_cfg {
u32 esdhc_base;
u32 no_snoop;
u32 clk_enable;
+ u32 is_usdhc;
};
#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_IMX_MMC)