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| author | Anish Trivedi <anish@freescale.com> | 2011-05-05 13:16:17 -0500 |
|---|---|---|
| committer | Anish Trivedi <anish@freescale.com> | 2011-05-10 11:38:23 -0500 |
| commit | c53f846a0b72a22f65f07b9eb6638168cc7004a9 (patch) | |
| tree | 771deedcdd90af9bb725b474ddc10219f86cf061 /include/fsl_esdhc.h | |
| parent | 6fc284a6a40dff807f1598e1c3ebda6cfb28cc8f (diff) | |
| download | u-boot-imx-c53f846a0b72a22f65f07b9eb6638168cc7004a9.zip u-boot-imx-c53f846a0b72a22f65f07b9eb6638168cc7004a9.tar.gz u-boot-imx-c53f846a0b72a22f65f07b9eb6638168cc7004a9.tar.bz2 | |
ENGR00142995 MX50: Enable uSDHC instead of eSDHC for SDR mode
On SD3 on MX50, there is an option to choose eSDHC or uSDHC controller.
By default eSDHC is selected. However, eSDHC shows some borderline timing
in SDR mode at 50 MHz, whereas uSDHC shows borderline timing in DDR mode
at 50 MHz. Therefore, add a compile time option to uboot for MX50 to
select uSDHC in SDR mode or eSDHC in DDR mode on SD3 port.
By default the compile time option, CONFIG_MX50_ENABLE_USDHC_SDR,
is commented out in the include/configs/mx50_<board>.h file to
select eSDHC with DDR mode enabled. Uncomment the define to select
uSDHC with only SDR mode enabled.
Also increased max frequency supported by ESDHC to 52 MHz instead
of 50 MHz.
Signed-off-by: Anish Trivedi <anish@freescale.com>
Diffstat (limited to 'include/fsl_esdhc.h')
| -rw-r--r-- | include/fsl_esdhc.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index e32d7d2..1787407 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -2,7 +2,7 @@ * FSL SD/MMC Defines *------------------------------------------------------------------- * - * Copyright (C) 2007-2008, 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2007-2008, 2010-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -34,6 +34,8 @@ #define SYSCTL_TIMEOUT_MASK 0x000f0000 #define SYSCTL_CLOCK_MASK 0x0000fff0 #define SYSCTL_RSTA 0x01000000 +#define SYSCTL_RSTC 0x02000000 +#define SYSCTL_RSTD 0x04000000 #define SYSCTL_SDCLKEN 0x00000008 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 |