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| author | Ye.Li <B37916@freescale.com> | 2015-03-23 17:33:43 +0800 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2015-04-29 15:03:07 +0800 |
| commit | 76885e14fa8aa562fd2f02c53f1b5a5784678e51 (patch) | |
| tree | 8d274945fe057b9c17cb12095b59b04bc0cecbc0 /include/fsl_ddrc_version.h | |
| parent | 0d631cb912e3c75b8c140cc483c40c3c5984d2d6 (diff) | |
| download | u-boot-imx-76885e14fa8aa562fd2f02c53f1b5a5784678e51.zip u-boot-imx-76885e14fa8aa562fd2f02c53f1b5a5784678e51.tar.gz u-boot-imx-76885e14fa8aa562fd2f02c53f1b5a5784678e51.tar.bz2 | |
MLK-10448-6 imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
1. Add DDR script v1.04 for i.MX6DQP SABREAUTO board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit e0b316f071aa17c8e41a50f395346ab9f012e665)
Conflicts:
board/freescale/mx6qsabreauto/mx6qsabreauto.c
boards.cfg
Diffstat (limited to 'include/fsl_ddrc_version.h')
0 files changed, 0 insertions, 0 deletions