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| author | York Sun <yorksun@freescale.com> | 2014-12-08 15:30:55 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-01-23 22:29:13 -0600 |
| commit | dda3b610eee9dcd433627202584ded417327dd51 (patch) | |
| tree | de7d6037e6730f3fd9bc2baa086dd74f449d0fd6 /include/fsl_ddr.h | |
| parent | 37b608a52dcb13312a4f7ccea199cd6bac76d298 (diff) | |
| download | u-boot-imx-dda3b610eee9dcd433627202584ded417327dd51.zip u-boot-imx-dda3b610eee9dcd433627202584ded417327dd51.tar.gz u-boot-imx-dda3b610eee9dcd433627202584ded417327dd51.tar.bz2 | |
arm/ls1021a: Add workaround for DDR erratum A008378
Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/fsl_ddr.h')
| -rw-r--r-- | include/fsl_ddr.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 675557a..3286c95 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -23,9 +23,15 @@ #ifdef CONFIG_SYS_FSL_DDR_LE #define ddr_in32(a) in_le32(a) #define ddr_out32(a, v) out_le32(a, v) +#define ddr_setbits32(a, v) setbits_le32(a, v) +#define ddr_clrbits32(a, v) clrbits_le32(a, v) +#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set) #else #define ddr_in32(a) in_be32(a) #define ddr_out32(a, v) out_be32(a, v) +#define ddr_setbits32(a, v) setbits_be32(a, v) +#define ddr_clrbits32(a, v) clrbits_be32(a, v) +#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set) #endif #define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR |