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| author | York Sun <yorksun@freescale.com> | 2014-02-10 13:59:42 -0800 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-02-21 11:06:13 -0500 |
| commit | 4e5b1bd0dff216b00d7ce9a5201dfe173805a06c (patch) | |
| tree | d8f8e7ffda3f504d4d98b6f494f0c73eed1196fc /include/fsl_ddr.h | |
| parent | 9c89614d3f1ea510d7fcb4a2b438fb3e0d58392c (diff) | |
| download | u-boot-imx-4e5b1bd0dff216b00d7ce9a5201dfe173805a06c.zip u-boot-imx-4e5b1bd0dff216b00d7ce9a5201dfe173805a06c.tar.gz u-boot-imx-4e5b1bd0dff216b00d7ce9a5201dfe173805a06c.tar.bz2 | |
driver/ddr: Change Freescale ARM DDR driver to support both big and little endian
Initially it was believed the DDR controller on Freescale ARM would have
big endian. But some platform will have little endian.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/fsl_ddr.h')
| -rw-r--r-- | include/fsl_ddr.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index e03f9db..72c0b2e 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -14,6 +14,14 @@ #include <common_timing_params.h> +#ifdef CONFIG_SYS_FSL_DDR_LE +#define ddr_in32(a) in_le32(a) +#define ddr_out32(a, v) out_le32(a, v) +#else +#define ddr_in32(a) in_be32(a) +#define ddr_out32(a, v) out_be32(a, v) +#endif + #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* * Bind the main DDR setup driver's generic names @@ -93,6 +101,7 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); +void board_add_ram_info(int use_default); /* processor specific function */ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, |