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authorvijay rai <vijay.rai@freescale.com>2014-04-15 11:34:12 +0530
committerYork Sun <yorksun@freescale.com>2014-04-22 17:58:52 -0700
commit0c12a1592c49c4fccea1df3eac9bf769aa1bd503 (patch)
treec598d47adacfb706974232736d5ccf68c36fc789 /include/e500.h
parentb0615f0bd22abc575824a0e20d1192913b77e282 (diff)
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powerpc/85xx: Enhance get_sys_info() to check clocking mode
T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/e500.h')
-rw-r--r--include/e500.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/e500.h b/include/e500.h
index 0c24326..5884a22 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -24,6 +24,9 @@ typedef struct
#ifdef CONFIG_SYS_DPAA_PME
unsigned long freq_pme;
#endif
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+ unsigned char diff_sysclk;
+#endif
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */