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author | Tom Rini <trini@konsulko.com> | 2016-09-27 12:47:25 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2016-09-27 12:47:25 -0400 |
commit | 40e1236afeeacdadfa3865f70fc7e3b8016acbe2 (patch) | |
tree | a915b83d54beceb8a5c4fa424c0bcb6df56238d8 /include/dt-bindings/memory/tegra210-mc.h | |
parent | 6d5565608f385b89f528ecf5680410cdc6cf63e9 (diff) | |
parent | 8e5d804f890b32959cc9d9f9349ccd2ff4a744a0 (diff) | |
download | u-boot-imx-40e1236afeeacdadfa3865f70fc7e3b8016acbe2.zip u-boot-imx-40e1236afeeacdadfa3865f70fc7e3b8016acbe2.tar.gz u-boot-imx-40e1236afeeacdadfa3865f70fc7e3b8016acbe2.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-tegra
Diffstat (limited to 'include/dt-bindings/memory/tegra210-mc.h')
-rw-r--r-- | include/dt-bindings/memory/tegra210-mc.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h new file mode 100644 index 0000000..d1731bc --- /dev/null +++ b/include/dt-bindings/memory/tegra210-mc.h @@ -0,0 +1,36 @@ +#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H +#define DT_BINDINGS_MEMORY_TEGRA210_MC_H + +#define TEGRA_SWGROUP_PTC 0 +#define TEGRA_SWGROUP_DC 1 +#define TEGRA_SWGROUP_DCB 2 +#define TEGRA_SWGROUP_AFI 3 +#define TEGRA_SWGROUP_AVPC 4 +#define TEGRA_SWGROUP_HDA 5 +#define TEGRA_SWGROUP_HC 6 +#define TEGRA_SWGROUP_NVENC 7 +#define TEGRA_SWGROUP_PPCS 8 +#define TEGRA_SWGROUP_SATA 9 +#define TEGRA_SWGROUP_MPCORE 10 +#define TEGRA_SWGROUP_ISP2 11 +#define TEGRA_SWGROUP_XUSB_HOST 12 +#define TEGRA_SWGROUP_XUSB_DEV 13 +#define TEGRA_SWGROUP_ISP2B 14 +#define TEGRA_SWGROUP_TSEC 15 +#define TEGRA_SWGROUP_A9AVP 16 +#define TEGRA_SWGROUP_GPU 17 +#define TEGRA_SWGROUP_SDMMC1A 18 +#define TEGRA_SWGROUP_SDMMC2A 19 +#define TEGRA_SWGROUP_SDMMC3A 20 +#define TEGRA_SWGROUP_SDMMC4A 21 +#define TEGRA_SWGROUP_VIC 22 +#define TEGRA_SWGROUP_VI 23 +#define TEGRA_SWGROUP_NVDEC 24 +#define TEGRA_SWGROUP_APE 25 +#define TEGRA_SWGROUP_NVJPG 26 +#define TEGRA_SWGROUP_SE 27 +#define TEGRA_SWGROUP_AXIAP 28 +#define TEGRA_SWGROUP_ETR 29 +#define TEGRA_SWGROUP_TSECB 30 + +#endif |