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| author | Simon Glass <sjg@chromium.org> | 2015-04-14 21:03:19 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-05-13 09:24:00 -0700 |
| commit | 3d7cf4192f045d9003c80bc937b18a6169eabbcf (patch) | |
| tree | 08a4632777c99c982235f920358f2367c049ce70 /include/dm | |
| parent | bd328eb38274ffaf04caaa8a6ecc09b7e19a650e (diff) | |
| download | u-boot-imx-3d7cf4192f045d9003c80bc937b18a6169eabbcf.zip u-boot-imx-3d7cf4192f045d9003c80bc937b18a6169eabbcf.tar.gz u-boot-imx-3d7cf4192f045d9003c80bc937b18a6169eabbcf.tar.bz2 | |
dm: core: Sort the uclasses
Sort uclasses into alphabetical order and tidy up the comments.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'include/dm')
| -rw-r--r-- | include/dm/uclass-id.h | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 08f1bad..b17528d 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -22,31 +22,31 @@ enum uclass_id { UCLASS_I2C_EMUL, /* sandbox I2C device emulator */ UCLASS_PCI_EMUL, /* sandbox PCI device emulator */ UCLASS_USB_EMUL, /* sandbox USB bus device emulator */ - UCLASS_SIMPLE_BUS, + UCLASS_SIMPLE_BUS, /* bus with child devices */ - /* U-Boot uclasses start here */ + /* U-Boot uclasses start here - in alphabetical order */ + UCLASS_CPU, /* CPU, typically part of an SoC */ + UCLASS_CROS_EC, /* Chrome OS EC */ + UCLASS_ETH, /* Ethernet device */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ - UCLASS_SERIAL, /* Serial UART */ - UCLASS_SPI, /* SPI bus */ - UCLASS_SPI_GENERIC, /* Generic SPI flash target */ - UCLASS_SPI_FLASH, /* SPI flash */ - UCLASS_CROS_EC, /* Chrome OS EC */ - UCLASS_THERMAL, /* Thermal sensor */ UCLASS_I2C, /* I2C bus */ - UCLASS_I2C_GENERIC, /* Generic I2C device */ UCLASS_I2C_EEPROM, /* I2C EEPROM device */ + UCLASS_I2C_GENERIC, /* Generic I2C device */ + UCLASS_LPC, /* x86 'low pin count' interface */ + UCLASS_MASS_STORAGE, /* Mass storage device */ UCLASS_MOD_EXP, /* RSA Mod Exp device */ + UCLASS_PCH, /* x86 platform controller hub */ UCLASS_PCI, /* PCI bus */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */ - UCLASS_PCH, /* x86 platform controller hub */ - UCLASS_ETH, /* Ethernet device */ - UCLASS_LPC, /* x86 'low pin count' interface */ + UCLASS_RTC, /* Real time clock device */ + UCLASS_SERIAL, /* Serial UART */ + UCLASS_SPI, /* SPI bus */ + UCLASS_SPI_GENERIC, /* Generic SPI flash target */ + UCLASS_SPI_FLASH, /* SPI flash */ + UCLASS_THERMAL, /* Thermal sensor */ UCLASS_USB, /* USB bus */ - UCLASS_USB_HUB, /* USB hub */ UCLASS_USB_DEV_GENERIC, /* USB generic device */ - UCLASS_MASS_STORAGE, /* Mass storage device */ - UCLASS_CPU, /* CPU, typically part of an SoC */ - UCLASS_RTC, /* Real time clock device */ + UCLASS_USB_HUB, /* USB hub */ UCLASS_COUNT, UCLASS_INVALID = -1, |