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| author | Jon Loeliger <jdl@freescale.com> | 2008-06-06 10:48:31 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2008-06-06 10:48:31 -0500 |
| commit | 1a247ba7fa5fb09f56892a09a990f03ce564b3e2 (patch) | |
| tree | 9dab0ef013cc6dc7883454808ecf6ba4d7a7a94e /include/dm9161.h | |
| parent | 2c289e320dcfb3760e99cf1d765cb067194a1202 (diff) | |
| parent | 8155efbd7ae9c65564ca98affe94631d612ae088 (diff) | |
| download | u-boot-imx-1a247ba7fa5fb09f56892a09a990f03ce564b3e2.zip u-boot-imx-1a247ba7fa5fb09f56892a09a990f03ce564b3e2.tar.gz u-boot-imx-1a247ba7fa5fb09f56892a09a990f03ce564b3e2.tar.bz2 | |
Merge commit 'wd/master'
Diffstat (limited to 'include/dm9161.h')
| -rw-r--r-- | include/dm9161.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/dm9161.h b/include/dm9161.h index d5d0e8d..218f15c 100644 --- a/include/dm9161.h +++ b/include/dm9161.h @@ -15,7 +15,7 @@ /* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */ -#define DM9161_BMCR 0 /* Basic Mode Control Register */ +#define DM9161_BMCR 0 /* Basic Mode Control Register */ #define DM9161_BMSR 1 /* Basic Mode Status Register */ #define DM9161_PHYID1 2 /* PHY Idendifier Register 1 */ #define DM9161_PHYID2 3 /* PHY Idendifier Register 2 */ @@ -32,7 +32,7 @@ /* --Bit definitions: DM9161_BMCR */ -#define DM9161_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */ +#define DM9161_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */ #define DM9161_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */ #define DM9161_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */ #define DM9161_AUTONEG (1 << 12) |