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authorYork Sun <yorksun@freescale.com>2012-08-17 08:22:37 +0000
committerAndy Fleming <afleming@freescale.com>2012-08-23 12:16:55 -0500
commit73b5396b25c52463aa71c782316e2d77a4b8d5ed (patch)
treeb6e82b205f1dc1a2d4a1eac37ec136cbe22822fa /include/ddr_spd.h
parent744713a6a3ca19c77585a9452829a2e2a55693ad (diff)
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powerpc/mpc8xxx: Add fine timing support for DDR3
When the DDR3 speed goes higher, we need to utilize fine offset from SPD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include/ddr_spd.h')
-rw-r--r--include/ddr_spd.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/include/ddr_spd.h b/include/ddr_spd.h
index a9230b9..9e74d87 100644
--- a/include/ddr_spd.h
+++ b/include/ddr_spd.h
@@ -221,7 +221,12 @@ typedef struct ddr3_spd_eeprom_s {
unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */
unsigned char therm_sensor; /* 32 Module Thermal Sensor */
unsigned char device_type; /* 33 SDRAM device type */
- unsigned char res_34_59[26]; /* 34-59 Reserved, General Section */
+ int8_t fine_tCK_min; /* 34 Fine offset for tCKmin */
+ int8_t fine_tAA_min; /* 35 Fine offset for tAAmin */
+ int8_t fine_tRCD_min; /* 36 Fine offset for tRCDmin */
+ int8_t fine_tRP_min; /* 37 Fine offset for tRPmin */
+ int8_t fine_tRC_min; /* 38 Fine offset for tRCmin */
+ unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */
/* Module-Specific Section: Bytes 60-116 */
union {