* Make sure HUSH is initialized for running auto-update scripts

* Make 5200 reset command _really_ reset the board, without running
  any other code after it

* Fix flash mapping and display on P3G4 board

* Patch by Kyle Harris, 15 Jul 2003:
  - add support for Intel IXP425 CPU
  - add support for IXDP425 eval board

2 files changed, 173 insertions, 2 deletions

diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h
index 7712384..b6ebc5f 100644
--- a/include/configs/P3G4.h
+++ b/include/configs/P3G4.h
@@ -154,7 +154,7 @@
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
 #define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xff800000
+#define CFG_FLASH_BASE		0xff000000
 #define CFG_RESET_ADDRESS	0xfff00100
 #define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
 #define CFG_MONITOR_BASE	TEXT_BASE
@@ -348,7 +348,7 @@
 #define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
 #define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
 
-#define CFG_EXTRA_FLASH_DEVICE	DEVICE0	/* extra flash at device 0 */
+#define CFG_EXTRA_FLASH_DEVICE	BOOT_DEVICE
 #define CFG_EXTRA_FLASH_WIDTH	2	/* 16 bit */
 #define CFG_BOOT_FLASH_WIDTH	2	/* 16 bit */
 
diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h
new file mode 100644
index 0000000..3d814d0
--- /dev/null
+++ b/include/configs/ixdp425.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2003
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * Configuation settings for the IXDP425 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_IXP425           1       /* This is an IXP425 CPU    */
+#define CONFIG_IXDP425          1       /* on an IXDP425 Board      */
+
+/***************************************************************
+ * U-boot generic defines start here.
+ ***************************************************************/
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#define CONFIG_INIT_CRITICAL            /* undef for developing */
+
+#undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN      (CFG_ENV_SIZE + 128*1024)
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE         115200
+
+#define CONFIG_COMMANDS         (CONFIG_CMD_DFL & ~CFG_CMD_NET)
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+/* These are u-boot generic parameters */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY        3
+#define CONFIG_ETHADDR          08:00:3e:26:0a:5b
+#define CONFIG_NETMASK          255.255.0.0
+#define CONFIG_IPADDR           192.168.0.21
+#define CONFIG_SERVERIP         192.168.0.250
+#define CONFIG_BOOTCOMMAND      "bootm 50040000"
+#define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
+#define CONFIG_CMDLINE_TAG      
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                            /* undef to save memory         */
+#define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
+#define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS             16              /* max number of command args   */
+#define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START       0x00400000      /* memtest works on     */
+#define CFG_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
+
+#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR           0x00010000      /* default load address */
+
+#define CFG_HZ                  3333333         /* spec says 66.666 MHz, but it appears to be 33 */
+                                                /* valid baudrates */
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
+#endif
+
+/***************************************************************
+ * Platform/Board specific defines start here.
+ ***************************************************************/
+
+/*
+ * Hardware drivers
+ */
+
+
+/*
+ * select serial console configuration
+ */
+#define CFG_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS    1          /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE       0x01000000 /* 16 MB */
+
+#define PHYS_FLASH_1            0x50000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE         0x00800000 /* 8 MB */
+#define PHYS_FLASH_BANK_SIZE    0x00800000 /* 8 MB Banks */
+#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
+
+#define CFG_DRAM_BASE           0x00000000
+#define CFG_DRAM_SIZE           0x01000000
+
+#define CFG_FLASH_BASE          PHYS_FLASH_1
+
+/*
+ * Expansion bus settings
+ */
+#define CFG_EXP_CS0				0xbcd23c42
+
+/*
+ * SDRAM settings
+ */
+#define CFG_SDR_CONFIG			0xd
+#define CFG_SDRAM_REFRESH_CNT 	0x81a
+
+/*
+ * GPIO settings
+ */
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT      128  	/* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT    (25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT    (25*CFG_HZ) /* Timeout for Flash Write */
+
+/* FIXME */
+#define	CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x20000)        /* Addr of Environment Sector   */
+#define CFG_ENV_SIZE            0x20000  /* Total Size of Environment Sector     */
+
+#endif  /* __CONFIG_H */