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author | Stefan Roese <sr@denx.de> | 2007-01-09 16:33:38 +0100 |
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committer | Stefan Roese <sr@denx.de> | 2007-01-09 16:33:38 +0100 |
commit | 7590da92b1c8bad5475e4b6cf18781248b966d9d (patch) | |
tree | 85b03056e87df75c9f1de6f401e3056a35e69502 /include/configs | |
parent | aeeced147c2ca52fbc674a6a7bd66ab1d80f245c (diff) | |
parent | f4eb54529bb3664c3a562e488b460fe075f79d67 (diff) | |
download | u-boot-imx-7590da92b1c8bad5475e4b6cf18781248b966d9d.zip u-boot-imx-7590da92b1c8bad5475e4b6cf18781248b966d9d.tar.gz u-boot-imx-7590da92b1c8bad5475e4b6cf18781248b966d9d.tar.bz2 |
Merge with git+ssh://sr@pollux.denx.org/home/sr/git/u-boot/denx/.git
Diffstat (limited to 'include/configs')
-rw-r--r-- | include/configs/alpr.h | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/include/configs/alpr.h b/include/configs/alpr.h index bbe6b76..49027da 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -166,8 +166,23 @@ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ + "ethprime=ppc_4xx_eth3\0" \ + "ethact=ppc_4xx_eth3\0" \ + "autoload=no\0" \ + "ipconfig=dhcp;setenv serverip 11.0.0.152\0" \ + "actkernel=kernel2\0" \ + "load_fpga=fpga load 0 ffe00000 10dd9a\0" \ + "mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \ + "rootfstype=jffs2 init=/sbin/init\0" \ + "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\ + ";bootm 200000\0" \ + "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \ + "addtty;bootm 200000\0" \ + "kernel1=run ipconfig load_fpga kernel1_mtd\0" \ + "kernel2=run ipconfig load_fpga kernel2_mtd\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTCOMMAND "run kernel2" #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ @@ -291,6 +306,8 @@ /*----------------------------------------------------------------------- * Definitions for GPIO setup *-----------------------------------------------------------------------*/ +#define CFG_GPIO_SHUTDOWN (0x80000000 >> 6) +#define CFG_GPIO_SSD_EMPTY (0x80000000 >> 9) #define CFG_GPIO_EREADY (0x80000000 >> 26) #define CFG_GPIO_REV0 (0x80000000 >> 14) #define CFG_GPIO_REV1 (0x80000000 >> 15) |