update the EB+MCF-EV123 board support

This patch updates the support for EB+MCF-EV123 board and needs
the [PATCH 1/2 V3] new video driver for bus vcxk framebuffers

* remove the board framebuffer driver
* use the common bus_vcxk framebuffer driver
* adds bmp support
* adds splashimage support
* fix serveral cosmetical errors

Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
[agust@denx.de: fixed some style issues before applying]
Signed-off-by: Anatolij Gustschin <agust@denx.de>

1 files changed, 97 insertions, 79 deletions

diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index a13db7c..a0b27a8 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -1,7 +1,7 @@
 /*
  * Configuation settings for the BuS EB+MCF-EV123 boards.
  *
- * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -25,16 +25,15 @@
 #ifndef _CONFIG_EB_MCF_EV123_H_
 #define _CONFIG_EB_MCF_EV123_H_
 
-#define  CONFIG_EB_MCF_EV123
-
 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
 
-/*
- * High Level Configuration Options (easy to change)
- */
+/*----------------------------------------------------------------------*
+ * High Level Configuration Options (easy to change)                    *
+ *----------------------------------------------------------------------*/
 
 #define	CONFIG_MCF52x2			/* define processor family */
 #define CONFIG_M5282			/* define processor type */
+#define CONFIG_EB_MCF_EV123
 
 #define CONFIG_MISC_INIT_R
 
@@ -43,29 +42,33 @@
 #define CONFIG_BAUDRATE 9600
 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
 
-#undef	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
+#undef	CONFIG_MONITOR_IS_IN_RAM		/* starts uboot direct */
 
 #define CONFIG_BOOTCOMMAND "printenv"
 
-/* Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
- */
+/*----------------------------------------------------------------------*
+ * Options								*
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_BOOT_RETRY_TIME	-1
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_SPLASH_SCREEN
+
+/*----------------------------------------------------------------------*
+ * Configuration for environment					*
+ * Environment is in the second sector of the first 256k of flash	*
+ *----------------------------------------------------------------------*/
+
 #ifndef CONFIG_MONITOR_IS_IN_RAM
 #define CONFIG_ENV_ADDR		0xF003C000	/* End of 256K */
 #define CONFIG_ENV_SECT_SIZE	0x4000
 #define CONFIG_ENV_IS_IN_FLASH	1
-/*
-#define CONFIG_ENV_IS_EMBEDDED	1
-#define CONFIG_ENV_ADDR_REDUND		0xF0018000
-#define CONFIG_ENV_SECT_SIZE_REDUND	0x4000
-*/
 #else
 #define CONFIG_ENV_ADDR		0xFFE04000
 #define CONFIG_ENV_SECT_SIZE	0x2000
 #define CONFIG_ENV_IS_IN_FLASH	1
 #endif
 
-
 /*
  * BOOTP options
  */
@@ -74,7 +77,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
-
 /*
  * Command line configuration.
  */
@@ -86,50 +88,20 @@
 
 #define CONFIG_MCFTMR
 
-#define CONFIG_MCFFEC
-#ifdef CONFIG_MCFFEC
-#	define CONFIG_NET_MULTI		1
-#	define CONFIG_MII		1
-#	define CONFIG_MII_INIT		1
-#	define CONFIG_SYS_DISCOVER_PHY
-#	define CONFIG_SYS_RX_ETH_BUFFER	8
-#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-#	define CONFIG_SYS_FEC0_PINMUX		0
-#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
-#	define MCFFEC_TOUT_LOOP		50000
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CONFIG_SYS_DISCOVER_PHY
-#		define FECDUPLEX	FULL
-#		define FECSPEED		_100BASET
-#	else
-#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#		endif
-#	endif			/* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-#ifdef CONFIG_MCFFEC
-#	define CONFIG_ETHADDR	00:CF:52:82:EB:01
-#	define CONFIG_IPADDR	192.162.1.2
-#	define CONFIG_NETMASK	255.255.255.0
-#	define CONFIG_SERVERIP	192.162.1.1
-#	define CONFIG_GATEWAYIP	192.162.1.1
-#	define CONFIG_OVERWRITE_ETHADDR_ONCE
-#endif				/* CONFIG_MCFFEC */
 
 #define CONFIG_BOOTDELAY	5
-#define CONFIG_SYS_PROMPT		"\nEV123 U-Boot> "
-#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_HUSH_PARSER
+#define CONFIG_SYS_PROMPT	"\nEV123 U-Boot> "
+#define	CONFIG_SYS_LONGHELP	1
 
 #if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size	*/
 #else
-#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size	*/
 #endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE 	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define	CONFIG_SYS_MAXARGS	16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
 
 #define CONFIG_SYS_LOAD_ADDR		0x20000
 
@@ -138,29 +110,53 @@
 /*#define CONFIG_SYS_DRAM_TEST		1 */
 #undef CONFIG_SYS_DRAM_TEST
 
-/* Clock and PLL Configuration */
+/*----------------------------------------------------------------------*
+ * Clock and PLL Configuration						*
+ *----------------------------------------------------------------------*/
 #define CONFIG_SYS_HZ			10000000
 #define	CONFIG_SYS_CLK			58982400       /* 9,8304MHz * 6 */
 
 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
 
-#define CONFIG_SYS_MFD			0x01	/* PLL Multiplication Factor Devider */
-#define CONFIG_SYS_RFD			0x00	/* PLL Reduce Frecuency Devider */
+#define CONFIG_SYS_MFD		0x01	/* PLL Multiplication Factor Devider */
+#define CONFIG_SYS_RFD		0x00	/* PLL Reduce Frecuency Devider */
 
-/*
+/*----------------------------------------------------------------------*
+ * Network								*
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_MCFFEC
+#define CONFIG_NET_MULTI		1
+#define CONFIG_MII			1
+#define CONFIG_MII_INIT			1
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#define CONFIG_SYS_FEC0_PINMUX		0
+#define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#define MCFFEC_TOUT_LOOP		50000
+
+#define CONFIG_ETHADDR			00:CF:52:82:EB:01
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/*-------------------------------------------------------------------------
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
  * You should know what you are doing if you make changes here.
- */
-#define	CONFIG_SYS_MBAR		0x40000000
+ *-----------------------------------------------------------------------*/
+
+#define	CONFIG_SYS_MBAR			0x40000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR       0x20000000
-#define CONFIG_SYS_INIT_RAM_END	0x10000		/* End of used area in internal SRAM	*/
-#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ *-----------------------------------------------------------------------*/
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_END		0x10000
+#define CONFIG_SYS_GBL_DATA_SIZE	64
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -169,18 +165,11 @@
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE1		0x00000000
-#define	CONFIG_SYS_SDRAM_SIZE1		16		/* SDRAM size in MB */
-
-/*
-#define CONFIG_SYS_SDRAM_BASE0		CONFIG_SYS_SDRAM_BASE1+CONFIG_SYS_SDRAM_SIZE1*1024*1024
-#define	CONFIG_SYS_SDRAM_SIZE0		16	*/	/* SDRAM size in MB */
+#define	CONFIG_SYS_SDRAM_SIZE1		16	/* SDRAM size in MB */
 
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_SDRAM_BASE1
 #define	CONFIG_SYS_SDRAM_SIZE		CONFIG_SYS_SDRAM_SIZE1
 
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
-#define	CONFIG_SYS_INT_FLASH_BASE	0xF0000000
-#define CONFIG_SYS_INT_FLASH_ENABLE	0x21
 
 /* If M5282 port is fully implemented the monitor base will be behind
  * the vector table. */
@@ -199,11 +188,16 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define	CONFIG_SYS_INT_FLASH_BASE	0xF0000000
+#define CONFIG_SYS_INT_FLASH_ENABLE	0x21
+
 #define	CONFIG_SYS_MAX_FLASH_SECT	35
 #define	CONFIG_SYS_MAX_FLASH_BANKS	2
 #define	CONFIG_SYS_FLASH_ERASE_TOUT	10000000
@@ -246,16 +240,40 @@
 #define CONFIG_SYS_PCDAT		0x0000000
 
 #define CONFIG_SYS_PEHLPAR		0xC0
-#define CONFIG_SYS_PUAPAR		0x0F		/* UA0..UA3 = Uart 0 +1 */
+#define CONFIG_SYS_PUAPAR		0x0F
 #define CONFIG_SYS_DDRUA		0x05
 #define CONFIG_SYS_PJPAR		0xFF
 
 /*-----------------------------------------------------------------------
- * CCM configuration
+ * VIDEO configuration
  */
 
-#define	CONFIG_SYS_CCM_SIZ		0
+#define CONFIG_VIDEO
 
-/*---------------------------------------------------------------------*/
+#ifdef CONFIG_VIDEO
+#define	CONFIG_VIDEO_VCXK			1
+
+#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN	2
+#define	CONFIG_SYS_VCXK_DOUBLEBUFFERED		1
+#define CONFIG_SYS_VCXK_BASE			CONFIG_SYS_CS3_BASE
+#define CONFIG_SYS_VCXK_AUTODETECT		1
+
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT	MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR		MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN		0x0001
+
+#define CONFIG_SYS_VCXK_ENABLE_PORT		MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_ENABLE_DDR		MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_ENABLE_PIN		0x0002
+
+#define CONFIG_SYS_VCXK_REQUEST_PORT		MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_REQUEST_DDR		MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_REQUEST_PIN		0x0004
+
+#define CONFIG_SYS_VCXK_INVERT_PORT		MCFGPIO_PORTE
+#define CONFIG_SYS_VCXK_INVERT_DDR		MCFGPIO_DDRE
+#define CONFIG_SYS_VCXK_INVERT_PIN		MCFGPIO_PORT2
+
+#endif /* CONFIG_VIDEO */
 #endif	/* _CONFIG_M5282EVB_H */
 /*---------------------------------------------------------------------*/