xpedite1k: Sync organization of board config with other X-ES boards

This change should have no functional effect

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 85 insertions, 74 deletions

diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h
index c67350a..391d041 100644
--- a/include/configs/XPEDITE1K.h
+++ b/include/configs/XPEDITE1K.h
@@ -38,26 +38,40 @@
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_pre_init	*/
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll */
 
-/* POST support */
-#define CONFIG_POST		(CONFIG_SYS_POST_RTC	| \
-				 CONFIG_SYS_POST_I2C)
+/*
+ * DDR config
+ */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS	{0x54}	/* SPD i2c spd addresses */
+#define CONFIG_VERY_BIG_RAM	1
 
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000		/* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE		0xff000000		/* start of FLASH */
-
-#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE		/* start of monitor */
-#define CONFIG_SYS_PCI_MEMBASE		0x80000000		/* mapped pci memory */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xe0000000		/* internal peripherals */
-#define CONFIG_SYS_ISRAM_BASE		0xc0000000		/* internal SRAM */
-#define CONFIG_SYS_PCI_BASE		0xd0000000		/* internal PCI regs */
-
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH */
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory */
+#define CONFIG_SYS_PERIPHERAL_BASE	0xe0000000	/* internal peripherals */
+#define CONFIG_SYS_ISRAM_BASE		0xc0000000	/* internal SRAM */
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs */
 #define CONFIG_SYS_NVRAM_BASE_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
 #define CONFIG_SYS_GPIO_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
 
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START	0x0400000
+#define CONFIG_SYS_MEMTEST_END		0x0C00000
+
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_RTC	| \
+				 CONFIG_SYS_POST_I2C)
+
+/*
+ * LED support
+ */
 #define USR_LED0	0x00000080
 #define USR_LED1	0x00000100
 #define USR_LED2	0x00000200
@@ -78,13 +92,14 @@ extern void out32(unsigned int, unsigned long);
 #define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
 #endif
 
-/* Initial RAM & stack pointer (placed in internal SRAM) */
+/*
+ * Use internal SRAM for initial stack
+ */
 #define CONFIG_SYS_TEMP_STACK_OCM	1
 #define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END		0x2000	/* End of used area in RAM */
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
-
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
@@ -92,19 +107,17 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)	/* Reserve 128 kB for malloc */
 
-/* Serial Port */
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_BAUDRATE		9600
+/*
+ * Serial Port
+ */
 #define CONFIG_SYS_BAUDRATE_TABLE \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
-
-/* RTC: STMicro M41T00 */
-#define CONFIG_RTC_M41T11		1
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+#define CONFIG_BAUDRATE			9600
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
- * FLASH related
+ * NOR flash configuration
  */
 #define CONFIG_SYS_MAX_FLASH_BANKS	3
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 }
@@ -118,45 +131,54 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
 
-/* DDR SDRAM */
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS	{0x54}	/* SPD i2c spd addresses */
-#define CONFIG_VERY_BIG_RAM	1
-
-/* I2C */
+/*
+ * I2C
+ */
 #define CONFIG_HARD_I2C			1	/* I2C with hardware support */
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7f
 #define CONFIG_SYS_I2C_NOPROBES	{0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69}
 
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128k (one sector) for env */
-#define CONFIG_ENV_SIZE		0x8000
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
-
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+/* I2C EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
-#define CONFIG_LOADS_ECHO	1		/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+/* I2C RTC: STMicro M41T00 */
+#define CONFIG_RTC_M41T11		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+
+/*
+ * PCI
+ */
+/* General PCI */
+#define CONFIG_PCI				/* include pci support */
+#define CONFIG_PCI_PNP				/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW			/* show pci devices on startup */
+#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_FORCE_PCI_CONV		/* Force PCI Conventional Mode */
 
+/*
+ * Networking options
+ */
 #define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management */
-#define CONFIG_PHY_ADDR		4	/* PHY address phy0 not populated */
-#define CONFIG_PHY2_ADDR	4	/* PHY address phy2 */
-#define CONFIG_PHY3_ADDR	8	/* PHY address phy3 */
-#define CONFIG_NET_MULTI	1
 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_PHY_RESET	1	/* reset phy upon startup */
 #define CONFIG_SYS_RX_ETH_BUFFER 32	/* Number of ethernet rx buffers & descriptors */
-
+#define CONFIG_ETHPRIME		"ppc_4xx_eth2"
+#define CONFIG_PHY_ADDR		4	/* PHY address phy0 not populated */
+#define CONFIG_PHY2_ADDR	4	/* PHY address phy2 */
 #define CONFIG_HAS_ETH2		1	/* add support for "eth2addr" */
+#define CONFIG_PHY3_ADDR	8	/* PHY address phy3 */
 #define CONFIG_HAS_ETH3		1	/* add support for "eth3addr" */
 
 /* BOOTP options */
@@ -166,7 +188,7 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_BOOTP_HOSTNAME
 
 /*
- * Command line configuration
+ * Command configuration
  */
 #include <config_cmd_default.h>
 
@@ -175,7 +197,6 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
-#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
@@ -184,14 +205,14 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_SNTP
 
-#undef CONFIG_WATCHDOG			/* watchdog disabled */
-
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
@@ -201,29 +222,8 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-/*
- * PCI
- */
-/* General PCI */
-#define CONFIG_PCI				/* include pci support */
-#define CONFIG_PCI_PNP				/* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW			/* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
-#define CONFIG_SYS_PCI_FORCE_PCI_CONV		/* Force PCI Conventional Mode */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
 
 /*
  * For booting Linux, the board info and command line data
@@ -233,17 +233,28 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*
- * Internal Definitions
+ * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot */
 
+/*
+ * KGDB configuration
+ */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 
 /*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
  * Flash memory map:
  * fff80000 - ffffffff	U-Boot (512 KB)
  * fff40000 - fff7ffff	U-Boot Environment (256 KB)