Merge branch 'master' of git://git.denx.de/u-boot-arm

16 files changed, 379 insertions, 28 deletions

diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 4ed5514..83056b6 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -49,6 +49,9 @@
 #define CONFIG_SYS_CLKDIV_PBA			2
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index b258f2d..6416d17 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -73,6 +73,9 @@
  */
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h
index 2ef2552..a4d9b0b 100644
--- a/include/configs/atstk1003.h
+++ b/include/configs/atstk1003.h
@@ -73,6 +73,9 @@
  */
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
index 195be82..06bb5da 100644
--- a/include/configs/atstk1004.h
+++ b/include/configs/atstk1004.h
@@ -73,6 +73,9 @@
  */
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h
index f93118e..d3cbee6 100644
--- a/include/configs/atstk1006.h
+++ b/include/configs/atstk1006.h
@@ -73,6 +73,9 @@
  */
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index 049298c..9ef4523 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -1,5 +1,5 @@
 /*
- * CPUAT91 by (C) Copyright 2006 Eric Benard
+ * CPUAT91 by (C) Copyright 2006-2010 Eric Benard
  * eric@eukrea.com
  *
  * Configuration settings for the CPUAT91 board.
@@ -23,15 +23,12 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_AT91_LEGACY
+#ifndef _CONFIG_CPUAT91_H
+#define _CONFIG_CPUAT91_H
 
 #ifdef CONFIG_CPUAT91_RAM
 #define CONFIG_SKIP_LOWLEVEL_INIT	1
 #define CONFIG_SKIP_RELOCATE_UBOOT	1
-#define CONFIG_CPUAT91			1
 #else
 #define CONFIG_BOOTDELAY		1
 #endif
@@ -43,6 +40,7 @@
 
 #define CONFIG_ARM920T			1
 #define CONFIG_AT91RM9200		1
+#define CONFIG_CPUAT91			1
 
 #undef CONFIG_USE_IRQ
 #define USE_920T_MMU			1
@@ -89,16 +87,36 @@
 #undef CONFIG_USART0
 #undef CONFIG_USART1
 
-#define CONFIG_HARD_I2C			1
+#undef CONFIG_HARD_I2C
+#define CONFIG_SOFT_I2C			1
+#define AT91_PIN_SDA			(1<<25)
+#define AT91_PIN_SCL			(1<<26)
+
+#define CONFIG_SYS_I2C_INIT_BOARD	1
+#define	CONFIG_SYS_I2C_SPEED		50000
+#define CONFIG_SYS_I2C_SLAVE		0
+
+#define I2C_INIT	i2c_init_board();
+#define I2C_ACTIVE	writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
+#define I2C_TRISTATE	writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
+#define I2C_READ	((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
+#define I2C_SDA(bit)						\
+	if (bit)						\
+		writel(AT91_PMX_AA_TWD, &pio->pioa.sodr);	\
+	else							\
+		writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
+#define I2C_SCL(bit)						\
+	if (bit)						\
+		writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr);	\
+	else							\
+		writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
+
+#define I2C_DELAY	udelay(2500000/CONFIG_SYS_I2C_SPEED)
 
-#if defined(CONFIG_HARD_I2C)
-#define	CONFIG_SYS_I2C_SPEED			50000
-#define CONFIG_SYS_I2C_SLAVE			0
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	1
 #define	CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-#endif
 
 #define CONFIG_BOOTP_BOOTFILESIZE	1
 #define CONFIG_BOOTP_BOOTPATH		1
@@ -117,10 +135,8 @@
 #undef CONFIG_CMD_LOADS
 #undef CONFIG_CMD_NFS
 
-#if defined(CONFIG_HARD_I2C)
 #define CONFIG_CMD_EEPROM		1
 #define CONFIG_CMD_I2C			1
-#endif
 
 #define CONFIG_NR_DRAM_BANKS			1
 #define PHYS_SDRAM				0x20000000
@@ -148,6 +164,7 @@
 #define PHYS_FLASH_1				0x10000000
 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 #define CONFIG_SYS_MAX_FLASH_SECT		128
+#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
 
 #if defined(CONFIG_CMD_USB)
 #define CONFIG_USB_OHCI_NEW			1
@@ -206,7 +223,7 @@
 	"mtdparts=physmap-flash.0:"	\
 		"128k(u-boot)ro,"	\
 		"128k(u-boot-env),"	\
-		"1408k(kernel),"	\
+		"1792k(kernel),"	\
 		"-(rootfs)"
 
 #define CONFIG_BOOTARGS 		\
@@ -221,13 +238,13 @@
 		"1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 "	\
 		"10000000 ${filesize}\0"				\
 	"flui=tftp 21000000 cpuat91/uImage; protect off 10040000 "	\
-		"1019ffff; erase 10040000 1019ffff; cp.b 21000000 "	\
+		"1019ffff; erase 10040000 101fffff; cp.b 21000000 "	\
 		"10040000 ${filesize}\0"				\
 	"flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off "	\
-		"101a0000 10ffffff; erase 101a0000 10ffffff; cp.b "	\
-		"21000000 101A0000 ${filesize}\0"			\
+		"10200000 10ffffff; erase 10200000 10ffffff; cp.b "	\
+		"21000000 10200000 ${filesize}\0"			\
 	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"		\
 	"flashboot=run ramargs;bootm 10040000\0"			\
 	"netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;"		\
 		"bootm 21000000\0"
-#endif	/* __CONFIG_H */
+#endif	/* _CONFIG_CPUAT91_H */
diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h
index 739ff0d..1c381c7 100644
--- a/include/configs/favr-32-ezkit.h
+++ b/include/configs/favr-32-ezkit.h
@@ -70,6 +70,9 @@
  */
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h
index 0c70af5..8ca04ea 100644
--- a/include/configs/hammerhead.h
+++ b/include/configs/hammerhead.h
@@ -47,6 +47,9 @@
 #define CONFIG_SYS_CLKDIV_PBA			2
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h
new file mode 100644
index 0000000..29c534c
--- /dev/null
+++ b/include/configs/jadecpu.h
@@ -0,0 +1,291 @@
+/*
+ * (C) Copyright 2010
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * Configuation settings for the jadecpu board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MB86R0x
+#define CONFIG_MB86R0x_IOCLK	get_bus_freq(0)
+#define CONFIG_SYS_HZ		1000
+
+#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+/*
+ * Environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"gs_fast_boot=setenv bootdelay 5\0" \
+	"gs_slow_boot=setenv bootdelay 10\0" \
+	"bootcmd=mw.l 0x40000000 0 1024; usb start;" \
+		"fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \
+		"bootelf 0x40000000\0" \
+	""
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+#define BOARD_LATE_INIT		1
+
+/*
+ * Compressions
+ */
+#define CONFIG_LZO
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * Serial
+ */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE		(-4)
+#define CONFIG_SYS_NS16550_CLK			get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1			0xfffe1000	/* UART 0 */
+#define CONFIG_SYS_NS16550_COM2			0xfff50000	/* UART 2 */
+#define CONFIG_SYS_NS16550_COM3			0xfff51000	/* UART 3 */
+#define CONFIG_SYS_NS16550_COM4			0xfff43000	/* UART 4 */
+
+#define CONFIG_CONS_INDEX	4
+
+/*
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE	0x02000000
+#define CONFIG_SMC911X_16_BIT
+
+/*
+ * Video
+ */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_MB86R0xGDC
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (800*480 + 256*4 + 10*1024)
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define VIDEO_KBD_INIT_FCT		0
+#define VIDEO_TSTC_FCT			serial_tstc
+#define VIDEO_GETC_FCT			serial_getc
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_CMD_BMP		1
+#define CONFIG_CMD_CAN		1
+#define CONFIG_CMD_DHCP		1
+#define CONFIG_CMD_ELF		1
+#define CONFIG_CMD_FAT		1
+#define CONFIG_CMD_PING		1
+#define CONFIG_CMD_USB		1
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_REGS_BASE       0xFFF81000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME       "mb86r0x"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  1
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x40000000	/* Start address of DDRRAM */
+#define PHYS_SDRAM_SIZE	0x08000000	/* 128 megs */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		0x10000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_SIZE		(128 * 1024)
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER	1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1	/* ~10x faster */
+
+#define CONFIG_SYS_LOAD_ADDR		0x40000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM + (512*1024))
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM + PHYS_SDRAM_SIZE)
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT	"jade> "
+#define CONFIG_SYS_CBSIZE	256
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP	1
+#define CONFIG_CMDLINE_EDITING	1
+
+#define CONFIG_PREBOOT  ""
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"delaygs"
+#define CONFIG_AUTOBOOT_STOP_STR	"stopgs"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x400000 - 0x8000)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+/*
+ * Clock reset generator init
+ */
+#define CONFIG_SYS_CRG_CRHA_INIT		0xffff
+#define CONFIG_SYS_CRG_CRPA_INIT		0xffff
+#define CONFIG_SYS_CRG_CRPB_INIT		0xfffe
+#define CONFIG_SYS_CRG_CRHB_INIT		0xffff
+#define CONFIG_SYS_CRG_CRAM_INIT		0xffef
+
+/*
+ * Memory controller settings
+ */
+#define CONFIG_SYS_MEMC_MCFMODE0_INIT	0x00000001	/* 16bit */
+#define CONFIG_SYS_MEMC_MCFMODE2_INIT	0x00000001	/* 16bit */
+#define CONFIG_SYS_MEMC_MCFMODE4_INIT	0x00000021	/* 16bit, Page*/
+#define CONFIG_SYS_MEMC_MCFTIM0_INIT	0x16191008
+#define CONFIG_SYS_MEMC_MCFTIM2_INIT	0x03061008
+#define CONFIG_SYS_MEMC_MCFTIM4_INIT	0x03061804
+#define CONFIG_SYS_MEMC_MCFAREA0_INIT	0x000000c0	/* 0x0c000000 1MB */
+#define CONFIG_SYS_MEMC_MCFAREA2_INIT	0x00000020	/* 0x02000000 1MB */
+#define CONFIG_SYS_MEMC_MCFAREA4_INIT	0x001f0000	/* 0x10000000 32 MB */
+
+/*
+ * DDR2 controller init settings
+ */
+#define CONFIG_SYS_DDR2_DRIMS_INIT	0x5555
+#define CONFIG_SYS_CCNT_CDCRC_INIT_1	0x00000002
+#define CONFIG_SYS_CCNT_CDCRC_INIT_2	0x00000003
+#define CONFIG_SYS_DDR2_DRIC1_INIT	0x003f
+#define CONFIG_SYS_DDR2_DRIC2_INIT	0x0000
+#define CONFIG_SYS_DDR2_DRCA_INIT	0xc124	/* 512Mbit DDR2SDRAM x 2 */
+#define CONFIG_SYS_DDR2_DRCM_INIT	0x0032
+#define CONFIG_SYS_DDR2_DRCST1_INIT	0x3418
+#define CONFIG_SYS_DDR2_DRCST2_INIT	0x6e32
+#define CONFIG_SYS_DDR2_DRCR_INIT	0x0141
+#define CONFIG_SYS_DDR2_DRCF_INIT	0x0002
+#define CONFIG_SYS_DDR2_DRASR_INIT	0x0001
+#define CONFIG_SYS_DDR2_DROBS_INIT	0x0001
+#define CONFIG_SYS_DDR2_DROABA_INIT	0x0103
+#define CONFIG_SYS_DDR2_DRIBSODT1_INIT	0x003F
+#define CONFIG_SYS_DDR2_DROS_INIT	0x0001
+
+/*
+ * DRAM init sequence
+ */
+
+/* PALL Command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_1	0x0017
+#define CONFIG_SYS_DDR2_INIT_DRIC2_1	0x0400
+
+/* EMR(2) command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_2	0x0006
+#define CONFIG_SYS_DDR2_INIT_DRIC2_2	0x0000
+
+/* EMR(3) command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_3	0x0007
+#define CONFIG_SYS_DDR2_INIT_DRIC2_3	0x0000
+
+/* EMR(1) command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_4	0x0005
+#define CONFIG_SYS_DDR2_INIT_DRIC2_4	0x0000
+
+/* MRS command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_5	0x0004
+#define CONFIG_SYS_DDR2_INIT_DRIC2_5	0x0532
+
+/* PALL command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_6	0x0017
+#define CONFIG_SYS_DDR2_INIT_DRIC2_6	0x0400
+
+/* REF command 1 */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_7	0x000f
+#define CONFIG_SYS_DDR2_INIT_DRIC2_7	0x0000
+
+/* MRS command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_8	0x0004
+#define CONFIG_SYS_DDR2_INIT_DRIC2_8	0x0432
+
+/* EMR(1) command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_9	0x0005
+#define CONFIG_SYS_DDR2_INIT_DRIC2_9	0x0380
+
+/* EMR(1) command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_10	0x0005
+#define CONFIG_SYS_DDR2_INIT_DRIC2_10	0x0002
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index e085f4a..dbb2531 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -3,7 +3,7 @@
  * Stelian Pop <stelian.pop@leadtechdesign.com>
  * Lead Tech Design <www.leadtechdesign.com>
  *
- * (C) Copyright 2009
+ * (C) Copyright 2009-2010
  * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
  * esd electronic system design gmbh <www.esd.eu>
  *
@@ -31,13 +31,12 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_AT91_LEGACY
-
 /* Common stuff */
-#define CONFIG_SYS_HZ			1000	/* decrementer freq */
 #define CONFIG_MEESC			1	/* Board is esd MEESC */
 #define CONFIG_ARM926EJS		1	/* This is an ARM926EJS Core */
 #define CONFIG_AT91SAM9263		1	/* It's an AT91SAM9263 SoC */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	16000000/* 16.0 MHz crystal */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq */
 #define CONFIG_DISPLAY_BOARDINFO	1
 #define CONFIG_DISPLAY_CPUINFO		1	/* display cpu info and speed */
 #define CONFIG_PREBOOT				/* enable preboot variable */
@@ -85,11 +84,11 @@
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_LOADS
 #undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_USB
 
 #define CONFIG_CMD_PING				1
 #define CONFIG_CMD_DHCP				1
 #define CONFIG_CMD_NAND				1
+#define CONFIG_CMD_USB				1
 
 /* LED */
 #define CONFIG_AT91_LED				1
@@ -121,9 +120,9 @@
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
-
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTD, 15
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 22
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
 #endif
 
 /* Ethernet */
@@ -133,6 +132,17 @@
 #define CONFIG_NET_RETRY_COUNT			20
 #undef CONFIG_RESET_PHY_R
 
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW			1
+#define CONFIG_DOS_PARTITION			1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE			1
+#define CONFIG_CMD_FAT				1
+
 #define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
 
 #define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h
index 36488b3..6ed9e75 100644
--- a/include/configs/mimc200.h
+++ b/include/configs/mimc200.h
@@ -51,6 +51,9 @@
 #define CONFIG_SYS_CLKDIV_PBA			2
 #define CONFIG_SYS_CLKDIV_PBB			1
 
+/* Reserve VM regions for SDRAM, NOR flash and FRAM */
+#define CONFIG_SYS_NR_VM_REGIONS		3
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index ae5a791..71553f9 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -158,6 +158,7 @@
 /*
  * Board NAND Info.
  */
+#define CONFIG_SYS_NAND_QUIET_TEST	1
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
 							/* to access nand */
@@ -183,6 +184,7 @@
 	"loadaddr=0x82000000\0" \
 	"usbtty=cdc_acm\0" \
 	"console=ttyS2,115200n8\0" \
+	"mpurate=500\0" \
 	"vram=12M\0" \
 	"dvimode=1024x768MR-16@60\0" \
 	"defaultdisplay=dvi\0" \
@@ -191,6 +193,7 @@
 	"nandroot=/dev/mtdblock4 rw\0" \
 	"nandrootfstype=jffs2\0" \
 	"mmcargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
 		"vram=${vram} " \
 		"omapfb.mode=dvi:${dvimode} " \
 		"omapfb.debug=y " \
@@ -198,6 +201,7 @@
 		"root=${mmcroot} " \
 		"rootfstype=${mmcrootfstype}\0" \
 	"nandargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
 		"vram=${vram} " \
 		"omapfb.mode=dvi:${dvimode} " \
 		"omapfb.debug=y " \
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 3a3b389..a0e0f24 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -129,6 +129,7 @@
 /*
  * Board NAND Info.
  */
+#define CONFIG_SYS_NAND_QUIET_TEST	1
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
 							/* to access nand */
@@ -153,6 +154,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"console=ttyS2,115200n8\0" \
+	"mpurate=500\0" \
 	"vram=12M\0" \
 	"dvimode=1024x768MR-16@60\0" \
 	"defaultdisplay=dvi\0" \
@@ -161,6 +163,7 @@
 	"nandroot=/dev/mtdblock4 rw\0" \
 	"nandrootfstype=jffs2\0" \
 	"mmcargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
 		"vram=${vram} " \
 		"omapfb.mode=dvi:${dvimode} " \
 		"omapfb.debug=y " \
@@ -168,6 +171,7 @@
 		"root=${mmcroot} " \
 		"rootfstype=${mmcrootfstype}\0" \
 	"nandargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
 		"vram=${vram} " \
 		"omapfb.mode=dvi:${dvimode} " \
 		"omapfb.debug=y " \
diff --git a/include/configs/otc570.h b/include/configs/otc570.h
index fb0f576..4a1cede 100644
--- a/include/configs/otc570.h
+++ b/include/configs/otc570.h
@@ -35,6 +35,7 @@
 #define CONFIG_OTC570			1	/* Board is esd OTC570 */
 #define CONFIG_ARM926EJS		1	/* This is an ARM926EJS Core */
 #define CONFIG_AT91SAM9263		1	/* It's an AT91SAM9263 SoC */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	16000000/* 16.0 MHz crystal */
 #define CONFIG_SYS_HZ			1000	/* decrementer freq */
 #define CONFIG_DISPLAY_BOARDINFO	1
 #define CONFIG_DISPLAY_CPUINFO		1	/* display cpu info and speed */
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index c8ea8fd..dc01ceb 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -30,7 +30,7 @@
 /* High Level Configuration Options */
 #define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
 #define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
-#define CONFIG_S5PC1XX		1	/* which is in a S5PC1XX Family */
+#define CONFIG_S5P		1	/* which is in a S5P Family */
 #define CONFIG_S5PC110		1	/* which is in a S5PC110 */
 #define CONFIG_MACH_GONI	1	/* working with Goni */
 
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 76a47c4..595d174 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -34,7 +34,7 @@
  */
 #define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
 #define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
-#define CONFIG_S5PC1XX		1	/* which is in a S5PC1XX Family */
+#define CONFIG_S5P		1	/* which is in a S5P Family */
 #define CONFIG_S5PC100		1	/* which is in a S5PC100 */
 #define CONFIG_SMDKC100		1	/* working with SMDKC100 */