Patch by Yuli Barcohen, 19 Apr 2004:

- Rename DUET_ADS to MPC885ADS
- Rename CONFIG_DUET to CONFIG_MPC885_FAMILY
- Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY
- Clean up FADS family port to use the new defines

4 files changed, 29 insertions, 46 deletions

diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h
index 916272d..df20965 100644
--- a/include/configs/ADS860.h
+++ b/include/configs/ADS860.h
@@ -26,15 +26,17 @@
 
 #define CONFIG_BAUDRATE		38400	/* Console baudrate */
 
-/* CFG_8XX_FACT * CFG_8XX_XIN = 50 MHz */
 #if 0
-#define CFG_8XX_XIN		32768	/* 32.768 kHz input frequency	*/
-#define CFG_8XX_FACT		0x5F6	/* Multiply by 1526 */
+#define CFG_8XX_FACT		1526	/* 32.768 kHz crystal on XTAL/EXTAL */
 #else
-#define CFG_8XX_XIN		4000000	/* 4 MHz input frequency	*/
-#define CFG_8XX_FACT		12	/* Multiply by 12 */
+#define CFG_8XX_FACT		12	/* 4 MHz oscillator on EXTCLK */
 #endif
 
+#define CFG_PLPRCR  (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+		PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+#define CONFIG_DRAM_50MHZ		1
+
 #define CONFIG_COMMANDS (CONFIG_CMD_DFL   \
 			 | CFG_CMD_DHCP   \
 			 | CFG_CMD_IMMAP  \
@@ -42,13 +44,9 @@
 			 | CFG_CMD_PING   \
 			)
 
-#define CONFIG_DRAM_50MHZ		1
 
 #include "fads.h"
 
-#define CFG_PLPRCR  (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
-		PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
 #define CFG_PC_IDE_RESET	((ushort)0x0008)    /* PC 12	*/
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/FADS860T.h b/include/configs/FADS860T.h
index e57571b..18de6b0 100644
--- a/include/configs/FADS860T.h
+++ b/include/configs/FADS860T.h
@@ -27,21 +27,19 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 
 #if 0 /* old FADS */
-# define CFG_8XX_FACT		12		/* Multiply by 12 */
-# define CFG_8XX_XIN		4000000		/* 4 MHz in	*/
+# define CFG_8XX_FACT		12	/* 4 MHz oscillator on EXTCLK */
 #else /* new FADS */
-# define CFG_8XX_FACT		10		/* Multiply by 10 */
-# define CFG_8XX_XIN		5000000		/* 5 MHz in	*/
+# define CFG_8XX_FACT		10	/* 5 MHz oscillator on EXTCLK */
 #endif
 
+#define CFG_PLPRCR  (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+		PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
 #define CONFIG_DRAM_50MHZ		1
 #define CONFIG_SDRAM_50MHZ              1
 
 #include "fads.h"
 
-#define CFG_PLPRCR	(((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
-			 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
 #ifdef USE_REAL_FLASH_VALUES
 /*
  * These values fit our FADS860T ...
@@ -53,6 +51,6 @@
 #define CFG_BR0_PRELIM	0x02800001  /* Real values for the board */
 #endif
 
-#define CFG_DAUGHTERBOARD /* FADS has processor-specfic daughterboard */
+#define CFG_DAUGHTERBOARD /* FADS has processor-specific daughterboard */
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h
index a6e2606..565f9bb 100644
--- a/include/configs/MPC86xADS.h
+++ b/include/configs/MPC86xADS.h
@@ -33,19 +33,14 @@
 #undef	CONFIG_8xx_CONS_NONE
 #define CONFIG_BAUDRATE		38400
 
-# define CFG_8XX_FACT		5		/* Multiply by 5	*/
-# define CFG_8XX_XIN		10000000	/* 10 MHz in	*/
+#define CONFIG_8xx_OSCLK	10000000 /* 10MHz oscillator on EXTCLK  */
 
 #define CONFIG_DRAM_50MHZ       1
 #define CONFIG_SDRAM_50MHZ      1
 
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		14-22
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control
- */
-#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS)
-
 #include "fads.h"
 
+#define CFG_OR5_PRELIM		0xFFFF8110	/* 64Kbyte address space */
+#define CFG_BR5_PRELIM		(CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/DUET_ADS.h b/include/configs/MPC885ADS.h
index 8a40257..7f0b06a 100644
--- a/include/configs/DUET_ADS.h
+++ b/include/configs/MPC885ADS.h
@@ -11,7 +11,7 @@
 #define __CONFIG_H
 
 /* Board type */
-#define CONFIG_DUET_ADS	        1	/* Duet (MPC87x/88x) ADS */
+#define CONFIG_MPC885ADS	        1	/* Duet (MPC87x/88x) ADS */
 #define CONFIG_FADS		1	/* We are FADS compatible (more or less) */
 
 #define CONFIG_MPC885 		1	/* MPC885 CPU (Duet family) */
@@ -21,33 +21,25 @@
 #undef	CONFIG_8xx_CONS_NONE
 #define CONFIG_BAUDRATE		38400
 
-#define CFG_8XX_FACT		5		/* Multiply by 5	*/
-#define CFG_8XX_XIN		10000000	/* 10 MHz in	*/
+#define CONFIG_8xx_OSCLK	10000000 /* 10 MHz oscillator on EXTCLK  */
+
+#define CFG_PLPRCR		((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS)
 
 #define CONFIG_SDRAM_50MHZ      1
 
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		14-22
- *-----------------------------------------------------------------------
- * set the PLL, the low-power modes and the reset control
- */
-#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS)
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL   \
+			 | CFG_CMD_DHCP   \
+			 | CFG_CMD_IMMAP  \
+			 | CFG_CMD_MII    \
+			 | CFG_CMD_PING   \
+			)
 
 #include "fads.h"
 
-#define CFG_PHYDEV_ADDR		(BCSR_ADDR + 0x20000)
+#undef CFG_SCCR
+#define CFG_SCCR	(SCCR_TBS|SCCR_EBDF11)
 
 #define CFG_OR5_PRELIM		0xFFFF8110	/* 64Kbyte address space */
 #define CFG_BR5_PRELIM		(CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)
 
-#define BCSR5			(CFG_PHYDEV_ADDR + 0x300)
-
-#define BCSR5_MII2_EN		0x40
-#define BCSR5_MII2_RST		0x20
-#define BCSR5_T1_RST		0x10
-#define BCSR5_ATM155_RST	0x08
-#define BCSR5_ATM25_RST		0x04
-#define BCSR5_MII1_EN		0x02
-#define BCSR5_MII1_RST		0x01
-
 #endif	/* __CONFIG_H */