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| author | Shengzhou Liu <Shengzhou.Liu@nxp.com> | 2016-08-26 18:30:39 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-09-14 14:08:22 -0700 |
| commit | b9e745bbe2562fda710d668dc9cef46e0b23049f (patch) | |
| tree | 202c8a38ec99f44e4182be83aed654ac1d27ccc2 /include/configs | |
| parent | 93a6d3284ca635496c6de097e49cadc8f62e6256 (diff) | |
| download | u-boot-imx-b9e745bbe2562fda710d668dc9cef46e0b23049f.zip u-boot-imx-b9e745bbe2562fda710d668dc9cef46e0b23049f.tar.gz u-boot-imx-b9e745bbe2562fda710d668dc9cef46e0b23049f.tar.bz2 | |
driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012a
This general MMDC driver adds basic support for Freescale MMDC
(Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8
LS1012A SoC for DDR3L, there will be a update to this driver to
support more flexible configuration if new features (DDR4, multiple
controllers/chip selections, etc) are implimented in future.
Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/
LS1012AFRDM.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/ls1012afrdm.h | 22 | ||||
| -rw-r--r-- | include/configs/ls1012aqds.h | 23 | ||||
| -rw-r--r-- | include/configs/ls1012ardb.h | 21 |
3 files changed, 54 insertions, 12 deletions
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 19ad194..136d648 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -9,19 +9,33 @@ #include "ls1012a_common.h" +/* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 - -#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x04180000 -#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x84180000 - +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +/* DDR board-specific timing parameters */ +#define CONFIG_MMDC_MDCTL 0x04180000 +#define CONFIG_MMDC_MDPDC 0x00030035 +#define CONFIG_MMDC_MDOTC 0x12554000 +#define CONFIG_MMDC_MDCFG0 0xbabf7954 +#define CONFIG_MMDC_MDCFG1 0xdb328f64 +#define CONFIG_MMDC_MDCFG2 0x01ff00db +#define CONFIG_MMDC_MDMISC 0x00001680 +#define CONFIG_MMDC_MDREF 0x0f3c8000 +#define CONFIG_MMDC_MDRWD 0x00002000 +#define CONFIG_MMDC_MDOR 0x00bf1023 +#define CONFIG_MMDC_MDASP 0x0000003f +#define CONFIG_MMDC_MPODTCTRL 0x0000022a +#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003 + + /* * USB */ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 75b60fa..b6d12dd 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -9,14 +9,31 @@ #include "ls1012a_common.h" - +/* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +/* DDR board-specific timing parameters */ +#define CONFIG_MMDC_MDCTL 0x05180000 +#define CONFIG_MMDC_MDPDC 0x00030035 +#define CONFIG_MMDC_MDOTC 0x12554000 +#define CONFIG_MMDC_MDCFG0 0xbabf7954 +#define CONFIG_MMDC_MDCFG1 0xdb328f64 +#define CONFIG_MMDC_MDCFG2 0x01ff00db +#define CONFIG_MMDC_MDMISC 0x00001680 +#define CONFIG_MMDC_MDREF 0x0f3c8000 +#define CONFIG_MMDC_MDRWD 0x00002000 +#define CONFIG_MMDC_MDOR 0x00bf1023 +#define CONFIG_MMDC_MDASP 0x0000003f +#define CONFIG_MMDC_MPODTCTRL 0x0000022a +#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003 -#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000 -#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000 /* * QIXIS Definitions diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index d3117e7..2076ce5 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -9,20 +9,31 @@ #include "ls1012a_common.h" - +/* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 - -#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000 -#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000 - #define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +/* DDR board-specific timing parameters */ +#define CONFIG_MMDC_MDCTL 0x05180000 +#define CONFIG_MMDC_MDPDC 0x00030035 +#define CONFIG_MMDC_MDOTC 0x12554000 +#define CONFIG_MMDC_MDCFG0 0xbabf7954 +#define CONFIG_MMDC_MDCFG1 0xdb328f64 +#define CONFIG_MMDC_MDCFG2 0x01ff00db +#define CONFIG_MMDC_MDMISC 0x00001680 +#define CONFIG_MMDC_MDREF 0x0f3c8000 +#define CONFIG_MMDC_MDRWD 0x00002000 +#define CONFIG_MMDC_MDOR 0x00bf1023 +#define CONFIG_MMDC_MDASP 0x0000003f +#define CONFIG_MMDC_MPODTCTRL 0x0000022a +#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003 + /* * USB */ |