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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2015-08-17 19:54:48 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-08-28 12:33:14 -0400 |
| commit | 401f2d91acac2b455dbaf222982ad461d5a2e43e (patch) | |
| tree | 14c53e624a07da45d7ed2e45b833d36a6a3916e7 /include/configs | |
| parent | a85da21f7527e70a2b81d71aa73d318fb354e912 (diff) | |
| download | u-boot-imx-401f2d91acac2b455dbaf222982ad461d5a2e43e.zip u-boot-imx-401f2d91acac2b455dbaf222982ad461d5a2e43e.tar.gz u-boot-imx-401f2d91acac2b455dbaf222982ad461d5a2e43e.tar.bz2 | |
ARM: keystone2: configs: Move SP to end of u-boot section
Currently u-boot stack is defined at the beginning of MSMC RAM.
This is a problem for uart boot mode as ROM downloads directly to
starting of MSMC RAM.
Fixing it by moving stack to the end of u-boot section and shifting
SYS_TEXT_BASE to the start of MSMC RAM.
Updated division of MSMC RAM is shown below:
-----------------------------------------
| | | |
| U-Boot text |U-Boot | SPL text |
| download | Stack | Download + |
| | | SPL_BSS + |
| | | SPL_STACK |
-----------------------------------------
[1] [2] [3] [4]
[1] SYS_TEXT_BASE (Start of MSMC RAM)
[2] SPL_TEXT_BASE - GBL_DATA_SIZE
[3] SPL_TEXT_BASE
[4] END of SPL
[1] + [2] is at least 1M on all platforms, so no chance of overlap.
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/ti_armv7_keystone2.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index b441590..58c98ce 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -20,7 +20,7 @@ /* SoC Configuration */ #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_ARCH_TIMER -#define CONFIG_SYS_TEXT_BASE 0x0c001000 +#define CONFIG_SYS_TEXT_BASE 0x0c000000 #define CONFIG_SPL_TARGET "u-boot-spi.gph" #define CONFIG_SYS_DCACHE_OFF @@ -29,7 +29,7 @@ #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ #define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \ GENERATED_GBL_DATA_SIZE) /* SPL SPI Loader Configuration */ |