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| author | Ye Li <ye.li@nxp.com> | 2017-03-08 11:48:32 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 14:06:24 +0800 |
| commit | 126d2e1ac5b53fc32dbd0000b2a22c11bfbcd19c (patch) | |
| tree | fc942e85846581fd48810b2a3529813443060296 /include/configs | |
| parent | e4f53022a8b0c911144fa8ec43a13da5641016fc (diff) | |
| download | u-boot-imx-126d2e1ac5b53fc32dbd0000b2a22c11bfbcd19c.zip u-boot-imx-126d2e1ac5b53fc32dbd0000b2a22c11bfbcd19c.tar.gz u-boot-imx-126d2e1ac5b53fc32dbd0000b2a22c11bfbcd19c.tar.bz2 | |
MLK-14380-1 mx6ullarm2: Add mx6ull DDR3 ARM2 board codes
Move the mx6ull ddr3 arm2 board codes and defconfigs from v2016.03
as the base for converting to use DTB OF_CONTROL.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/mx6ull_ddr3_arm2.h | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/include/configs/mx6ull_ddr3_arm2.h b/include/configs/mx6ull_ddr3_arm2.h new file mode 100644 index 0000000..f612209 --- /dev/null +++ b/include/configs/mx6ull_ddr3_arm2.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6ULL_DDR3_ARM2_CONFIG_H +#define __MX6ULL_DDR3_ARM2_CONFIG_H + +#define CONFIG_DEFAULT_FDT_FILE "imx6ull-14x14-ddr3-arm2.dtb" + +#ifdef CONFIG_SYS_BOOT_QSPI +#define CONFIG_SYS_USE_QSPI +#define CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined CONFIG_SYS_BOOT_SPINOR +#define CONFIG_SYS_USE_SPINOR +#define CONFIG_ENV_IS_IN_SPI_FLASH +#elif defined CONFIG_SYS_BOOT_NAND +#define CONFIG_SYS_USE_NAND +#define CONFIG_ENV_IS_IN_NAND +#else +#ifndef CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK +#define CONFIG_SYS_USE_QSPI +#endif +#define CONFIG_ENV_IS_IN_MMC +#endif + +#define CONFIG_VIDEO +#define CONFIG_FSL_USDHC +#define BOOTARGS_CMA_SIZE "" + +#include "mx6ul_arm2.h" + +#define CONFIG_IOMUX_LPSR + +#define PHYS_SDRAM_SIZE SZ_1G + +/* + * TSC pins conflict with I2C1 bus, so after TSC + * hardware rework, need to disable i2c1 bus, also + * need to disable PMIC and ldo bypass check. + */ +#ifdef CONFIG_MX6ULL_DDR3_ARM2_TSC_REWORK +#undef CONFIG_LDO_BYPASS_CHECK +#undef CONFIG_SYS_I2C_MXC +#undef CONFIG_SYS_I2C +#undef CONFIG_CMD_I2C +#undef CONFIG_POWER_PFUZE100_I2C_ADDR +#undef CONFIG_POWER_PFUZE100 +#undef CONFIG_POWER_I2C +#undef CONFIG_POWER +#endif + +#ifdef CONFIG_SYS_USE_SPINOR +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_CS 0 +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE MII100 +#endif +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_FEC_DMA_MINALIGN 64 +#endif + +#endif |