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| author | Alexey Brodkin <abrodkin@synopsys.com> | 2015-02-03 13:58:13 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2015-02-09 16:41:20 +0300 |
| commit | 205e7a7b77726abeff57576e2ecf2c6d4dc07ccf (patch) | |
| tree | 5f3bae0b6a43d741cb1aabf10f541b6ec38b921e /include/configs | |
| parent | 5ff40f3d4226d45c78f3bb9db276f6685b24a89a (diff) | |
| download | u-boot-imx-205e7a7b77726abeff57576e2ecf2c6d4dc07ccf.zip u-boot-imx-205e7a7b77726abeff57576e2ecf2c6d4dc07ccf.tar.gz u-boot-imx-205e7a7b77726abeff57576e2ecf2c6d4dc07ccf.tar.bz2 | |
arc: select cache settings via menuconfig
This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.
It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/arcangel4-be.h | 1 | ||||
| -rw-r--r-- | include/configs/arcangel4.h | 1 | ||||
| -rw-r--r-- | include/configs/axs101.h | 4 | ||||
| -rw-r--r-- | include/configs/tb100.h | 1 |
4 files changed, 0 insertions, 7 deletions
diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h index a43590b..b0bc8bc 100644 --- a/include/configs/arcangel4-be.h +++ b/include/configs/arcangel4-be.h @@ -11,7 +11,6 @@ * CPU configuration */ #define CONFIG_SYS_BIG_ENDIAN -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ /* diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h index 565f70e..3268c56 100644 --- a/include/configs/arcangel4.h +++ b/include/configs/arcangel4.h @@ -10,7 +10,6 @@ /* * CPU configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ /* diff --git a/include/configs/axs101.h b/include/configs/axs101.h index b94687c..ff3fad3 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -10,12 +10,8 @@ /* * CPU configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ -/* NAND controller DMA doesn't work correctly with D$ enabled */ -#define CONFIG_SYS_DCACHE_OFF - /* * Board configuration */ diff --git a/include/configs/tb100.h b/include/configs/tb100.h index f353950..32675c4 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -12,7 +12,6 @@ /* * CPU configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ /* |