Merge remote-tracking branch 'u-boot/master'

33 files changed, 427 insertions, 400 deletions

diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 0d09f0e..45d1064 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -1,7 +1,7 @@
 /*
  * Configuation settings for the Freescale MCF5373 FireEngine board.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -59,7 +59,7 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
-#ifdef NANDFLASH_SIZE
+#ifdef CONFIG_NANDFLASH_SIZE
 #      define CONFIG_CMD_NAND
 #endif
 
@@ -208,7 +208,7 @@
 #	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
 #endif
 
-#ifdef NANDFLASH_SIZE
+#ifdef CONFIG_NANDFLASH_SIZE
 #	define CONFIG_SYS_MAX_NAND_DEVICE	1
 #	define CONFIG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
 #	define CONFIG_SYS_NAND_SIZE		1
@@ -264,9 +264,9 @@
 #define CONFIG_SYS_CS1_MASK		0x001f0001
 #define CONFIG_SYS_CS1_CTRL		0x002A3780
 
-#ifdef NANDFLASH_SIZE
+#ifdef CONFIG_NANDFLASH_SIZE
 #define CONFIG_SYS_CS2_BASE		0x20000000
-#define CONFIG_SYS_CS2_MASK		((NANDFLASH_SIZE << 20) | 1)
+#define CONFIG_SYS_CS2_MASK		((CONFIG_NANDFLASH_SIZE << 20) | 1)
 #define CONFIG_SYS_CS2_CTRL		0x00001f60
 #endif
 
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 7f2761c..2d48dde 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -37,6 +37,24 @@
 
 #define CONFIG_MISC_INIT_R
 
+/* new uImage format support */
+#define CONFIG_FIT			1
+#define CONFIG_FIT_VERBOSE		1
+
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ESDHC_USE_PIO
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
 /*
  * On-board devices
  *
@@ -340,6 +358,19 @@
 #define CONFIG_SYS_I2C_OFFSET	0x3000
 #define CONFIG_SYS_I2C2_OFFSET	0x3100
 
+/*
+ * SPI on header J8
+ *
+ * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
+ * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_USE_SPIFLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#endif
 
 /*
  * Board info - revision and where boot from
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 1c0eb74..3169665 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -22,7 +22,7 @@
 
 /*
  * P2041 RDB board configuration file
- *
+ * Also supports P2040 RDB
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
@@ -36,6 +36,15 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #endif
 
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
 #define CONFIG_E500			/* BOOKE e500 family */
@@ -73,7 +82,7 @@
 #define CONFIG_ENV_OVERWRITE
 
 #ifdef CONFIG_SYS_NO_FLASH
-#ifndef CONFIG_RAMBOOT_PBL
+#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_NOWHERE
 #endif
 #else
@@ -104,8 +113,12 @@
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
 #elif defined(CONFIG_ENV_IS_NOWHERE)
-	#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SIZE		0x2000
 #else
 	#define CONFIG_ENV_IS_IN_FLASH
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE \
@@ -374,6 +387,35 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
 
 /*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000	/* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_FSL_ESPI
@@ -485,6 +527,16 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0xEF000000
diff --git a/include/configs/P3060QDS.h b/include/configs/P3060QDS.h
deleted file mode 100644
index 8006547..0000000
--- a/include/configs/P3060QDS.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * P3060 QDS board configuration file
- */
-#define CONFIG_P3060QDS
-#define CONFIG_PHYS_64BIT
-#define CONFIG_PPC_P3060
-#define CONFIG_FSL_QIXIS
-
-#define CONFIG_NAND_FSL_ELBC
-
-#define CONFIG_ICS307_REFCLK_HZ	25000000  /* ICS307 ref clk freq */
-
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_EON
-#define CONFIG_SPI_FLASH_SST
-
-#include "corenet_ds.h"
-
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-
-/* There is a PCA9547 8-channel I2C-bus multiplexer on P3060QDS board */
-#define CONFIG_I2C_MUX
-#define CONFIG_I2C_MULTI_BUS
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 4a2e475..d6f2f5c 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -22,6 +22,7 @@
 
 /*
  * P4080 DS board configuration file
+ * Also supports P4040 DS
  */
 #define CONFIG_P4080DS
 #define CONFIG_PHYS_64BIT
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
index 4afc4f1..8625f76 100644
--- a/include/configs/P5020DS.h
+++ b/include/configs/P5020DS.h
@@ -22,7 +22,7 @@
 
 /*
  * P5020 DS board configuration file
- *
+ * Also supports P5010 DS
  */
 #define CONFIG_P5020DS
 #define CONFIG_PHYS_64BIT
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index a3752bc..263a5ad 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -193,6 +193,7 @@
 
 /* Defines for SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE		0x402F0400
 #define CONFIG_SPL_MAX_SIZE		(46 * 1024)
 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index f24b44d..8ddeff4 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -314,6 +314,8 @@
 
 /* Defines for SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_TEXT_BASE		0x40200800
 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 95f8d78..6980811 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -313,6 +313,8 @@
 
 /* Defines for SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_TEXT_BASE		0x40200800
 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
diff --git a/include/configs/apollon.h b/include/configs/apollon.h
deleted file mode 100644
index b8ca8a8..0000000
--- a/include/configs/apollon.h
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * (C) Copyright 2005-2008
- * Samsung Electronics,
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * Configuration settings for the 2420 Samsung Apollon board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARM1136		1 /* This is an arm1136 CPU core */
-#define CONFIG_OMAP		1 /* in a TI OMAP core */
-#define CONFIG_OMAP2420		1 /* which is in a 2420 */
-#define CONFIG_OMAP2420_APOLLON	1
-#define CONFIG_APOLLON		1
-#define CONFIG_APOLLON_PLUS	1 /* If you have apollon plus 1.x */
-
-#define CONFIG_ONENAND_U_BOOT	y
-
-/* Clock config to target*/
-#define PRCM_CONFIG_I		1
-/* #define PRCM_CONFIG_II	1 */
-
-/* Boot method */
-/* uncomment if you use NOR boot */
-/* #define CONFIG_SYS_NOR_BOOT		1 */
-
-/* uncomment if you use NOR on CS3 */
-/* #define CONFIG_SYS_USE_NOR		1 */
-
-#ifdef CONFIG_SYS_NOR_BOOT
-#undef CONFIG_SYS_USE_NOR
-#define CONFIG_SYS_USE_NOR		1
-#endif
-
-/* uncommnet if you want to use UBI */
-#define CONFIG_SYS_USE_UBI
-
-#include <asm/arch/omap2420.h>	/* get chip and board defs */
-
-#define	V_SCLK	12000000
-
-/* input clock of PLL */
-/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
-#define	CONFIG_SYS_CLK_FREQ	V_SCLK
-
-#define	CONFIG_MISC_INIT_R
-
-#define	CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
-#define	CONFIG_SETUP_MEMORY_TAGS	1
-#define	CONFIG_INITRD_TAG	1
-#define	CONFIG_REVISION_TAG	1
-
-/*
- * Size of malloc() pool
- */
-#define	CONFIG_ENV_SIZE SZ_128K	/* Total Size of Environment Sector */
-#define CONFIG_ENV_SIZE_FLEX SZ_256K
-#define	CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + SZ_1M)
-
-/*
- * Hardware drivers
- */
-
-/*
- * SMC91c96 Etherent
- */
-#define	CONFIG_LAN91C96
-#define	CONFIG_LAN91C96_BASE	(APOLLON_CS1_BASE+0x300)
-#define	CONFIG_LAN91C96_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-#define	V_NS16550_CLK	(48000000)	/* 48MHz (APLL96/2) */
-
-#define	CONFIG_SYS_NS16550
-#define	CONFIG_SYS_NS16550_SERIAL
-#define	CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define	CONFIG_SYS_NS16550_CLK	V_NS16550_CLK	/* 3MHz (1.5MHz*2) */
-#define	CONFIG_SYS_NS16550_COM1	OMAP2420_UART1
-
-/*
- * select serial console configuration
- */
-#define	CONFIG_SERIAL1	1	/* UART1 on H4 */
-
-/* allow to overwrite serial and ethaddr */
-#define	CONFIG_ENV_OVERWRITE
-#define	CONFIG_CONS_INDEX	1
-#define	CONFIG_BAUDRATE		115200
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include	<config_cmd_default.h>
-
-#define	CONFIG_CMD_DHCP
-#define	CONFIG_CMD_DIAG
-#define	CONFIG_CMD_ONENAND
-
-#ifdef CONFIG_SYS_USE_UBI
-#define	CONFIG_CMD_JFFS2
-#define	CONFIG_CMD_UBI
-#define	CONFIG_RBTREE
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define CONFIG_MTD_PARTITIONS
-#endif
-
-#undef	CONFIG_CMD_SOURCE
-
-#ifndef	CONFIG_SYS_USE_NOR
-# undef	CONFIG_CMD_FLASH
-# undef	CONFIG_CMD_IMLS
-#endif
-
-#define	CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
-
-#define	CONFIG_BOOTDELAY	1
-
-#define	CONFIG_NETMASK	255.255.255.0
-#define	CONFIG_IPADDR	192.168.116.25
-#define	CONFIG_SERVERIP	192.168.116.1
-#define	CONFIG_BOOTFILE	"uImage"
-#define	CONFIG_ETHADDR	00:0E:99:00:24:20
-
-#ifdef CONFIG_APOLLON_PLUS
-#define CONFIG_SYS_MEM	"mem=64M"
-#else
-#define CONFIG_SYS_MEM	"mem=128"
-#endif
-
-#ifdef CONFIG_SYS_USE_UBI
-#define CONFIG_SYS_UBI "ubi.mtd=4"
-#else
-#define CONFIG_SYS_UBI ""
-#endif
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw " CONFIG_SYS_MEM \
-	" console=ttyS0,115200n8" \
-	" ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:" \
-	"apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2 " \
-	CONFIG_SYS_UBI
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"Image=tftp 0x80008000 Image; go 0x80008000\0"			\
-	"zImage=tftp 0x80180000 zImage; go 0x80180000\0"		\
-	"uImage=tftp 0x80180000 uImage; bootm 0x80180000\0"		\
-	"uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0"		\
-	"xloader=tftp 0x80180000 x-load.bin; "				\
-	" cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0"		\
-	"syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0"	\
-	"syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0"	\
-	"norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0"	\
-	"oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0" \
-	"onesyncboot=run syncmode oneboot\0"				\
-	"updateb=tftp 0x80180000 u-boot-onenand.bin; "			\
-	" onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0" \
-	"ubi=setenv bootargs ${bootargs} ubi.mtd=4 ${mtdparts}; run uImage\0" \
-	"bootcmd=run uboot\0"
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP	/* undef to save memory */
-#define	CONFIG_SYS_PROMPT	"Apollon # "
-#define	CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define	CONFIG_SYS_MAXARGS	16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define	CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define	CONFIG_SYS_MEMTEST_START	(OMAP2420_SDRC_CS0)
-#define	CONFIG_SYS_MEMTEST_END		(OMAP2420_SDRC_CS0+SZ_31M)
-
-/* default load address */
-#define	CONFIG_SYS_LOAD_ADDR	(OMAP2420_SDRC_CS0)
-
-/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
- * or by 32KHz clk, or from external sig. This rate is divided by a local
- * divisor.
- */
-#define	CONFIG_SYS_TIMERBASE	OMAP2420_GPT2
-#define	CONFIG_SYS_PTV		7	/* 2^(PTV+1) */
-#define	CONFIG_SYS_HZ		((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define	CONFIG_NR_DRAM_BANKS	1	/* CS1 may or may not be populated */
-#define	PHYS_SDRAM_1		OMAP2420_SDRC_CS0
-#define	PHYS_SDRAM_1_SIZE	SZ_128M
-#define	PHYS_SDRAM_2		OMAP2420_SDRC_CS1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#ifdef	CONFIG_SYS_USE_NOR
-/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */
-# define	CONFIG_SYS_FLASH_BASE		0x18000000
-# define	CONFIG_SYS_MAX_FLASH_BANKS	1
-# define	CONFIG_SYS_MAX_FLASH_SECT	1024
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* Flash memory is CFI compliant */
-# define	CONFIG_SYS_FLASH_CFI	1
-# define	CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
-/* Use buffered writes (~10x faster) */
-/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */
-/* Use h/w sector protection*/
-# define	CONFIG_SYS_FLASH_PROTECTION	1
-
-#else	/* !CONFIG_SYS_USE_NOR */
-# define	CONFIG_SYS_NO_FLASH	1
-#endif	/* CONFIG_SYS_USE_NOR */
-
-/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */
-#define	CONFIG_SYS_ONENAND_BASE	0x00000000
-#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* U-Boot image size */
-#define	CONFIG_ENV_IS_IN_ONENAND	1
-#define CONFIG_ENV_ADDR		0x00020000
-#define CONFIG_ENV_ADDR_FLEX	0x00040000
-
-#ifdef CONFIG_SYS_USE_UBI
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"onenand0=onenand"
-#define MTDPARTS_DEFAULT	"mtdparts=onenand:128k(bootloader),"	\
-					"128k(params),"			\
-					"2m(kernel),"			\
-					"16m(rootfs),"			\
-					"32m(fs),"			\
-					"-(ubifs)"
-#endif
-
-#define PHYS_SRAM			0x4020F800
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR 	PHYS_SRAM
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h
new file mode 100644
index 0000000..f85374f
--- /dev/null
+++ b/include/configs/atngw100mkii.h
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * Configuration settings for the AVR32 Network Gateway
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_AVR32
+#define CONFIG_AT32AP
+#define CONFIG_AT32AP7000
+#define CONFIG_ATNGW100MKII
+
+/*
+ * Timer clock frequency. We're using the CPU-internal COUNT register
+ * for this, so this is equivalent to the CPU core clock frequency
+ */
+#define CONFIG_SYS_HZ			1000
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
+ * and the PBA bus to run at 1/4 the PLL frequency.
+ */
+#define CONFIG_PLL
+#define CONFIG_SYS_POWER_MANAGER
+#define CONFIG_SYS_OSC0_HZ		20000000
+#define CONFIG_SYS_PLL0_DIV		1
+#define CONFIG_SYS_PLL0_MUL		7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
+ */
+#define CONFIG_SYS_CLKDIV_CPU		0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
+ */
+#define CONFIG_SYS_CLKDIV_HSB		1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBA		2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBB		1
+
+/* Reserve VM regions for NOR flash, NAND flash and SDRAM */
+#define CONFIG_SYS_NR_VM_REGIONS	3
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CONFIG_SYS_PLL0_OPT		0x04
+
+#define CONFIG_USART_BASE		ATMEL_BASE_USART1
+#define CONFIG_USART_ID			1
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"root=mtd:main rootfstype=jffs2"
+#define CONFIG_BOOTCOMMAND						\
+	"fsload 0x10400000 /uImage; bootm"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+
+/*
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_NET_MULTI
+
+/*
+ * BOOTP/DHCP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_MACB
+#define CONFIG_PORTMUX_PIO
+#define CONFIG_SYS_NR_PIOS		5
+#define CONFIG_SYS_HSDRAMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1
+#define CONFIG_ATMEL_SPI
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+
+#define CONFIG_SYS_DCACHE_LINESZ	32
+#define CONFIG_SYS_ICACHE_LINESZ	32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_PROTECTION
+
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_INTRAM_BASE		INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE		INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE		EBI_SDRAM_BASE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE			65536
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		(256*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN	(16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CONFIG_SYS_LOAD_ADDR		(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x1f00000)
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
index 91ab812..9b56e02 100644
--- a/include/configs/cam_enc_4xx.h
+++ b/include/configs/cam_enc_4xx.h
@@ -215,10 +215,11 @@
 
 /* Defines for SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_NAND_LOAD
 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_POST_MEM_SUPPORT
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index f8f7a82..f4f9bd1 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -31,13 +31,21 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
+#if defined(CONFIG_P3041DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
+#elif defined(CONFIG_P4080DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
+#elif defined(CONFIG_P5020DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
+#endif
 #endif
 
-#ifdef CONFIG_SRIOBOOT_SLAVE
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
-#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #define CONFIG_SYS_NO_FLASH
 #endif
@@ -77,7 +85,7 @@
 #define CONFIG_ENV_OVERWRITE
 
 #ifdef CONFIG_SYS_NO_FLASH
-#if !defined(CONFIG_SRIOBOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_ENV_IS_NOWHERE
 #endif
 #else
@@ -108,7 +116,7 @@
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIOBOOT_SLAVE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_IN_REMOTE
 #define CONFIG_ENV_ADDR		0xffe20000
 #define CONFIG_ENV_SIZE		0x2000
@@ -186,11 +194,7 @@
 #define CONFIG_DDR_SPD
 #define CONFIG_FSL_DDR3
 
-#ifdef CONFIG_P3060QDS
-#define CONFIG_SYS_SPD_BUS_NUM	0
-#else
 #define CONFIG_SYS_SPD_BUS_NUM	1
-#endif
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
@@ -389,51 +393,32 @@
 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
 
 /*
- * SRIOBOOT - MASTER
- */
-#ifdef CONFIG_SRIOBOOT_MASTER
-/* master port for srioboot*/
-#define CONFIG_SRIOBOOT_MASTER_PORT 0
-/* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */
-/*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000	/* 512K */
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull
-#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000	/* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
 /*
- * for slave UCODE instored in master memory space,
+ * for slave UCODE and ENV instored in master memory space,
  * PHYS must be aligned based on the SIZE
  */
-#define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull
-#define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull
-#define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000	/* 64K */
-/*
- * for slave ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull
-#define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull
-#define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000	/* 128K */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
 /* slave core release by master*/
-#define CONFIG_SRIOBOOT_SLAVE_HOLDOFF
-#define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */
-#endif
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 
 /*
- * SRIOBOOT - SLAVE
+ * SRIO_PCIE_BOOT - SLAVE
  */
-#ifdef CONFIG_SRIOBOOT_SLAVE
-/* slave port for srioboot */
-#define CONFIG_SRIOBOOT_SLAVE_PORT0
-/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
-#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
-		(0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 #endif
 
 /*
@@ -556,13 +541,13 @@
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SRIOBOOT_SLAVE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
  * in two corenet boards, slave's ucode could be stored in master's memory
  * space, the address can be mapped from slave TLB->slave LAW->
- * slave SRIO outbound window->master inbound window->master LAW->
- * the ucode address in master's NOR flash.
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
@@ -724,7 +709,7 @@
 
 #define CONFIG_BAUDRATE	115200
 
-#if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS)
+#ifdef CONFIG_P4080DS
 #define __USB_PHY_TYPE	ulpi
 #else
 #define __USB_PHY_TYPE	utmi
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 09a9660..ddd6155 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -380,6 +380,16 @@
 #ifndef CONFIG_DIRECT_NOR_BOOT
 /* defines for SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
+						CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
@@ -392,10 +402,9 @@
 /* Load U-Boot Image From MMC */
 #ifdef CONFIG_SPL_MMC_LOAD
 #define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SYS_MMC_U_BOOT_OFFS	0x75
-#define CONFIG_SYS_MMC_U_BOOT_SIZE	0x30000
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x75
+#undef CONFIG_SPL_SPI_SUPPORT
 #undef CONFIG_SPL_SPI_LOAD
 #endif
 
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index de75daf..2d2ee5f 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -303,6 +303,7 @@
 
 /* Defines for SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_NAND_SIMPLE
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 16f2d2a..46171b9 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -212,7 +212,6 @@
  * NAND FLASH driver setup
  */
 #define CONFIG_NAND_MXC
-#define CONFIG_NAND_MXC_V1_1
 #define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h
index 73ab4c8..c0e3ed3 100644
--- a/include/configs/hawkboard.h
+++ b/include/configs/hawkboard.h
@@ -60,9 +60,10 @@
 
 /* Spl */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_NAND_LOAD
 #define CONFIG_SPL_LIBGENERIC_SUPPORT	/* for udelay and __div64_32 for NAND */
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_LDSCRIPT		"board/$(BOARDDIR)/u-boot-spl-hawk.lds"
@@ -79,6 +80,7 @@
 #define CONFIG_MAX_RAM_BANK_SIZE	(512 << 20)
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 -\
 					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_MONITOR_LEN		0x60000
 
 /* memtest start addr */
 #define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1)
@@ -136,7 +138,6 @@
 #define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0xe0000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x60000
 #define CONFIG_SYS_NAND_U_BOOT_DST	0xc1180000
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h
index 5468a1a..b1071e8 100644
--- a/include/configs/igep00x0.h
+++ b/include/configs/igep00x0.h
@@ -295,6 +295,7 @@
 
 /* SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_TEXT_BASE		0x40200800
 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 733022e..359522a 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -359,6 +359,8 @@
 
 /* Defines for SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_NAND_SOFTECC
 
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 1266cf7..721cd90 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -115,19 +115,11 @@
 #endif
 
 /* timer */
-#ifdef XILINX_TIMER_BASEADDR
-# if (XILINX_TIMER_IRQ != -1)
-#  define CONFIG_SYS_TIMER_0		1
+#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
 #  define CONFIG_SYS_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
 #  define CONFIG_SYS_TIMER_0_IRQ	XILINX_TIMER_IRQ
-#  define FREQUENCE	XILINX_CLOCK_FREQ
-#  define CONFIG_SYS_TIMER_0_PRELOAD	( FREQUENCE/1000 )
-# endif
-#elif XILINX_CLOCK_FREQ
-# define CONFIG_XILINX_CLOCK_FREQ	XILINX_CLOCK_FREQ
-#else
-# error BAD CLOCK FREQ
 #endif
+
 /* FSL */
 /* #define	CONFIG_SYS_FSL_2 */
 /* #define	FSL_INTR_2	1 */
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 38b1546..69bd654 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -236,7 +236,6 @@
  * NAND FLASH driver setup
  */
 #define CONFIG_NAND_MXC
-#define CONFIG_NAND_MXC_V1_1
 #define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 782a4c5..f79f996 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -391,6 +391,7 @@
 
 /* Defines for SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_TEXT_BASE		0x40200800
 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
index d9578f4..2ef3aaa 100644
--- a/include/configs/omap3_evm_common.h
+++ b/include/configs/omap3_evm_common.h
@@ -273,6 +273,7 @@
 
 /* Defines for SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE		0x40200800
 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index dd4b2c0..f6d6f75 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -293,6 +293,7 @@
 
 /* Defines for SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_TEXT_BASE		0x40200800
 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index ee0c4b9..cbc9bdb 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -232,9 +232,11 @@
 
 /* Defines for SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE		0x40304350
 #define CONFIG_SPL_MAX_SIZE		(38 * 1024)
 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_DISPLAY_PRINT
 
 /*
  * 64 bytes before this address should be set aside for u-boot.img's
diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h
index 4f0a6c1..743edfd 100644
--- a/include/configs/omap5_evm.h
+++ b/include/configs/omap5_evm.h
@@ -229,9 +229,11 @@
 
 /* Defines for SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE		0x40300350
 #define CONFIG_SPL_MAX_SIZE		0x19000	/* 100K */
 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_DISPLAY_PRINT
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index a8882d4..b18f4a0 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -31,7 +31,7 @@
 #endif
 
 #if defined(CONFIG_P1020MBG)
-#define CONFIG_BOARDNAME "P1020MBG"
+#define CONFIG_BOARDNAME "P1020MBG-PC"
 #define CONFIG_P1020
 #define CONFIG_VSC7385_ENET
 #define CONFIG_SLIC
@@ -41,7 +41,7 @@
 #endif
 
 #if defined(CONFIG_P1020UTM)
-#define CONFIG_BOARDNAME "P1020UTM"
+#define CONFIG_BOARDNAME "P1020UTM-PC"
 #define CONFIG_P1020
 #define __SW_BOOT_MASK		0x03
 #define __SW_BOOT_NOR		0xe0
@@ -49,7 +49,7 @@
 #endif
 
 #if defined(CONFIG_P1020RDB)
-#define CONFIG_BOARDNAME "P1020RDB"
+#define CONFIG_BOARDNAME "P1020RDB-PC"
 #define CONFIG_NAND_FSL_ELBC
 #define CONFIG_P1020
 #define CONFIG_SPI_FLASH
@@ -64,7 +64,7 @@
 #endif
 
 #if defined(CONFIG_P1021RDB)
-#define CONFIG_BOARDNAME "P1021RDB"
+#define CONFIG_BOARDNAME "P1021RDB-PC"
 #define CONFIG_NAND_FSL_ELBC
 #define CONFIG_P1021
 #define CONFIG_QE
@@ -111,7 +111,7 @@
 #endif
 
 #if defined(CONFIG_P2020RDB)
-#define CONFIG_BOARDNAME "P2020RDB"
+#define CONFIG_BOARDNAME "P2020RDB-PCA"
 #define CONFIG_NAND_FSL_ELBC
 #define CONFIG_P2020
 #define CONFIG_SPI_FLASH
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 306c173..b8b9705 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -100,7 +100,12 @@
  */
 #define CONFIG_SYS_LONGHELP				/* undef to save memory */
 
-#define CONFIG_SYS_PROMPT		"qemu-mips # "	/* Monitor Command Prompt */
+/* Monitor Command Prompt */
+#if defined(CONFIG_SYS_LITTLE_ENDIAN)
+#define CONFIG_SYS_PROMPT		"qemu-mipsel # "
+#else
+#define CONFIG_SYS_PROMPT		"qemu-mips # "
+#endif
 
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_CMDLINE_EDITING
diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
index a3fc465..4bb5bbc 100644
--- a/include/configs/qi_lb60.h
+++ b/include/configs/qi_lb60.h
@@ -11,6 +11,7 @@
 #define __CONFIG_QI_LB60_H
 
 #define CONFIG_MIPS32		/* MIPS32 CPU core */
+#define CONFIG_SYS_LITTLE_ENDIAN
 #define CONFIG_JZSOC		/* Jz SoC */
 #define CONFIG_JZ4740		/* Jz4740 SoC */
 #define CONFIG_NAND_JZ4740
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index a13fd93..cbb6c7e 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -239,6 +239,8 @@
 
 /* Defines for SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_CONSOLE
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_NAND_SOFTECC
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 8a0deea..b3b5a3d 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -78,6 +78,7 @@
 #define CONFIG_MMC
 #define CONFIG_S5P_SDHCI
 #define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
 
 /* PWM */
 #define CONFIG_PWM
@@ -97,6 +98,21 @@
 #undef CONFIG_CMD_ONENAND
 #undef CONFIG_CMD_MTDPARTS
 #define CONFIG_CMD_MMC
+#define CONFIG_CMD_DFU
+
+/* FAT */
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+
+/* USB Samsung's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
+#define CONFIG_G_DNL_MANUFACTURER "Samsung"
 
 #define CONFIG_BOOTDELAY		1
 #define CONFIG_ZERO_BOOTDELAY_CHECK
@@ -107,6 +123,11 @@
 #define CONFIG_BOOTBLOCK		"10"
 #define CONFIG_ENV_COMMON_BOOT		"${console} ${meminfo}"
 
+#define CONFIG_DFU_ALT \
+	"dfu_alt_info=" \
+	"u-boot mmc 80 400;" \
+	"uImage fat 0 2\0" \
+
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
@@ -150,7 +171,8 @@
 	"mmcdev=0\0" \
 	"mmcbootpart=2\0" \
 	"mmcrootpart=3\0" \
-	"opts=always_resume=1"
+	"opts=always_resume=1\0" \
+	CONFIG_DFU_ALT
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
@@ -190,18 +212,28 @@
 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_CACHELINE_SIZE       32
 
-#include <asm/arch/gpio.h>
-/*
- * I2C Settings
- */
-#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7)
-#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6)
 
 #define CONFIG_SOFT_I2C
 #define CONFIG_SOFT_I2C_READ_REPEATED_START
+#define CONFIG_SYS_I2C_INIT_BOARD
 #define CONFIG_SYS_I2C_SPEED	50000
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS	7
+#define CONFIG_SOFT_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS	15
+
+#include <asm/arch/gpio.h>
+
+/* I2C PMIC */
+#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
+#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
+
+/* I2C FG */
+#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
+#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
+
+#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
+#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
+#define I2C_INIT multi_i2c_init()
 
 #define CONFIG_PMIC
 #define CONFIG_PMIC_I2C
@@ -210,6 +242,7 @@
 #define CONFIG_USB_GADGET
 #define CONFIG_USB_GADGET_S3C_UDC_OTG
 #define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
 
 /* LCD */
 #define CONFIG_EXYNOS_FB
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 63c98dc..00d02e8 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -271,6 +271,7 @@
 
 /* Defines for SPL */
 #define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_NAND_SIMPLE
 
 #define CONFIG_SPL_BOARD_INIT
diff --git a/include/configs/tx25.h b/include/configs/tx25.h
index c8a49bb..71b1d32 100644
--- a/include/configs/tx25.h
+++ b/include/configs/tx25.h
@@ -107,7 +107,6 @@
 
 /* NAND */
 #define CONFIG_NAND_MXC
-#define CONFIG_NAND_MXC_V1_1
 #define CONFIG_MXC_NAND_REGS_BASE	(0xBB000000)
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		(0xBB000000)