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| author | Paul Burton <paul.burton@imgtec.com> | 2013-11-08 11:18:50 +0000 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2013-11-09 17:21:01 +0100 |
| commit | baf37f06c5cc51d2b9d71a2c83d5d92de60203a9 (patch) | |
| tree | 7ad3945d47de4c1b5a7a1594b45f3b623a46df8c /include/configs | |
| parent | a257f6263b51321ecacc69ac1effbcbe2158fe15 (diff) | |
| download | u-boot-imx-baf37f06c5cc51d2b9d71a2c83d5d92de60203a9.zip u-boot-imx-baf37f06c5cc51d2b9d71a2c83d5d92de60203a9.tar.gz u-boot-imx-baf37f06c5cc51d2b9d71a2c83d5d92de60203a9.tar.bz2 | |
malta: support for coreFPGA6 boards
This patch adds support for running on Malta boards using coreFPGA6
core cards, including support for the msc01 system controller used
with them. The system controller is detected at runtime allowing one
U-boot binary to run on a Malta with either.
Due to the PCI I/O base differing between Maltas using gt64120 & msc01
system controllers, the UART setup is modified slightly. A second UART
is added so that there is one pointing at the correct address for each
system controller. The Malta board then defines its own
default_serial_console function to select the correct one at runtime.
The incorrect UART will simply not function.
Tested on:
- A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both
with and without an L2 cache.
- QEMU.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/malta.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/configs/malta.h b/include/configs/malta.h index d067d98..5e322f6 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -17,6 +17,7 @@ #define CONFIG_PCI #define CONFIG_PCI_GT64120 +#define CONFIG_PCI_MSC01 #define CONFIG_PCI_PNP #define CONFIG_PCNET @@ -76,7 +77,8 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK 115200 -#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_UART_BASE) +#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_GT_UART0_BASE) +#define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE) #define CONFIG_CONS_INDEX 1 /* |