Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts: cpu/arm1176/cpu.c cpu/arm1176/start.S cpu/arm_cortexa8/s5pc1xx/Makefile cpu/arm_cortexa8/s5pc1xx/clock.c drivers/serial/serial_s5p.c include/asm-arm/arch-s5pc1xx/clk.h include/asm-arm/arch-s5pc1xx/gpio.h include/asm-arm/arch-s5pc1xx/uart.h Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
author: Minkyu Kang <mk7.kang@samsung.com> 2010-04-19 10:26:18 +0900
committer: Minkyu Kang <mk7.kang@samsung.com> 2010-04-19 10:26:18 +0900
commit: 83653121d7382fccfe329cb732f77f116341ef1d (patch)
tree: 0b1ce6764252af15dfb2614372de98a44a7ec61f /include/configs
parent: 0f1f21a345e02a68ec16f7ab9e7dc687f9276089 (diff)
parent: 07739bcef5da07cc4a4edef8b91014ccc332eda3 (diff)
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128 files changed, 1700 insertions, 727 deletions
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 5cb0f1e..4cb8052 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -244,6 +244,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/B2.h b/include/configs/B2.h
index f51a261..ca7350d 100644
--- a/include/configs/B2.h
+++ b/include/configs/B2.h
@@ -207,7 +207,7 @@
 */
 
 /*
-	Linux TAGs (see lib_arm/armlinux.c)
+	Linux TAGs (see arch/arm/lib/armlinux.c)
 */
 #define CONFIG_CMDLINE_TAG
 #undef CONFIG_SETUP_MEMORY_TAGS
diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index 8c5a742..44befe9 100644
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -471,13 +471,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
-# define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-# define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-# define CONFIG_SYS_HID0_INIT		0
-# define CONFIG_SYS_HID0_FINAL		0
-#endif
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h
index e3e6e75..cdba81d 100644
--- a/include/configs/CANBT.h
+++ b/include/configs/CANBT.h
@@ -173,6 +173,7 @@
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index ae8494d..2b6786b 100644
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -224,6 +224,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index 5c88c47..9221211 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -207,6 +207,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index d131aea..3e7020d 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -256,6 +256,7 @@
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index 07c4e35..d3000f6 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -283,6 +283,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index c78552b..d376344 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -259,6 +259,7 @@
  * I2C EEPROM (CAT24WC32) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index 59e0778..07acab0 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -278,6 +278,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
index b2679e5..5b50bcf 100644
--- a/include/configs/CPCIISER4.h
+++ b/include/configs/CPCIISER4.h
@@ -189,6 +189,7 @@
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h
index 96bf161..9ab30ec 100644
--- a/include/configs/CRAYL1.h
+++ b/include/configs/CRAYL1.h
@@ -65,6 +65,7 @@
  #define CONFIG_ETHADDR          00:40:a6:80:14:5
  */
 #define CONFIG_HARD_I2C         1		/* hardware support for i2c */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SDRAM_BANK0		1
 #define CONFIG_SYS_I2C_SPEED		    400000	/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		    0x7F
diff --git a/include/configs/DP405.h b/include/configs/DP405.h
index 49ecb6f..4423f2a 100644
--- a/include/configs/DP405.h
+++ b/include/configs/DP405.h
@@ -174,6 +174,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/DU405.h b/include/configs/DU405.h
index cfb3023..8f1fc78 100644
--- a/include/configs/DU405.h
+++ b/include/configs/DU405.h
@@ -212,6 +212,7 @@
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
index 65dc235..830466f 100644
--- a/include/configs/DU440.h
+++ b/include/configs/DU440.h
@@ -169,6 +169,7 @@
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support    */
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged	        */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address  */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_I2C_MULTI_BUS    1
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index a0b27a8..880cb4e 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -208,6 +208,18 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DBWE | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h
index 61d8e20..3920d35 100644
--- a/include/configs/EP1C20.h
+++ b/include/configs/EP1C20.h
@@ -94,7 +94,8 @@
 /*------------------------------------------------------------------------
  * CONSOLE
  *----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART		1	/* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
 #define CONFIG_SYS_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
 #else
 #define CONFIG_SYS_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
@@ -123,14 +124,16 @@
  * TIMEBASE --
  *
  * The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
  *----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ			1000	/* Always 1000 */
 #define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
-#define CONFIG_SYS_NIOS_TMRMS		10		/* 10 msec per tick	*/
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ		3	/* Timer IRQ num	*/
+#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+		(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
 
 /*------------------------------------------------------------------------
  * STATUS LED -- Provides a simple blinking led. For Nios2 each board
diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h
index 41e64e6..bfbf8c1 100644
--- a/include/configs/EP1S10.h
+++ b/include/configs/EP1S10.h
@@ -92,7 +92,8 @@
 /*------------------------------------------------------------------------
  * CONSOLE
  *----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART		1	/* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
 #define CONFIG_SYS_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
 #else
 #define CONFIG_SYS_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
@@ -118,14 +119,16 @@
  * TIMEBASE --
  *
  * The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
  *----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ			1000	/* Always 1000 */
 #define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
-#define CONFIG_SYS_NIOS_TMRMS		10		/* 10 msec per tick	*/
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ		3	/* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+		(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
 
 /*------------------------------------------------------------------------
  * STATUS LED -- Provides a simple blinking led. For Nios2 each board
diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h
index 5b332e4..4d905fe 100644
--- a/include/configs/EP1S40.h
+++ b/include/configs/EP1S40.h
@@ -92,7 +92,8 @@
 /*------------------------------------------------------------------------
  * CONSOLE
  *----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART		1	/* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
 #define CONFIG_SYS_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
 #else
 #define CONFIG_SYS_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
@@ -118,14 +119,16 @@
  * TIMEBASE --
  *
  * The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
  *----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ			1000	/* Always 1000 */
 #define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
-#define CONFIG_SYS_NIOS_TMRMS		10		/* 10 msec per tick	*/
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ		3	/* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec) */
+#define CONFIG_SYS_NIOS_TMRCNT \
+		(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
 
 /*------------------------------------------------------------------------
  * STATUS LED -- Provides a simple blinking led. For Nios2 each board
diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h
index 023f33e..e07f9a1 100644
--- a/include/configs/ERIC.h
+++ b/include/configs/ERIC.h
@@ -54,6 +54,7 @@
 #endif					/* total size of a X1240 is 2048 bytes */
 
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
index 6819c3e..d2883eb 100644
--- a/include/configs/G2000.h
+++ b/include/configs/G2000.h
@@ -295,6 +295,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 9233523..01e0bc6 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -331,6 +331,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #if 0 /* test-only */
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #else
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index ea502d4..8c6d5ed 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -244,6 +244,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 5ef0b77..5d3a744 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -30,6 +30,7 @@
  */
 
 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* (more precisely a MPC5200 CPU) */
 #define CONFIG_ICECUBE		1	/* ... on IceCube board */
 
 #define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
@@ -47,7 +48,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 
-#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
 /*
  * PCI Mapping:
  * 0x40000000 - 0x4fffffff - PCI Memory
@@ -77,10 +77,6 @@
 #define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X		1
 
-#else
-#define CONFIG_MII		1
-#endif
-
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -169,7 +165,6 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#if defined(CONFIG_MPC5200)
 /*
  * IPB Bus clocking configuration.
  */
@@ -178,7 +173,6 @@
 #else
 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
-#endif /* CONFIG_MPC5200 */
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
@@ -338,13 +332,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #if defined(CONFIG_LITE5200B)
 #define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
diff --git a/include/configs/JSE.h b/include/configs/JSE.h
index 80c70e4..98f5661 100644
--- a/include/configs/JSE.h
+++ b/include/configs/JSE.h
@@ -217,6 +217,7 @@
 
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h
index 4b67c94..49a7378 100644
--- a/include/configs/KAREF.h
+++ b/include/configs/KAREF.h
@@ -132,6 +132,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C	      1		     /* I2C hardware support	*/
 #undef	CONFIG_SOFT_I2C			     /* I2C !bit-banged		*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED	      400000	     /* I2C speed 400kHz	*/
 #define CONFIG_SYS_I2C_SLAVE	      0x7F	     /* I2C slave address	*/
 #define CONFIG_SYS_I2C_NOPROBES      {0x69}	     /* Don't probe these addrs */
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 32123d2..e6632ac 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -158,7 +158,7 @@
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
 #define CONFIG_SYS_SDRAM_CFG1		0x43711630
 #define CONFIG_SYS_SDRAM_CFG2		0x56670000
 #define CONFIG_SYS_SDRAM_CTRL		0xE1002000
@@ -207,6 +207,19 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /* Chipselect bank definitions */
 /*
  * CS0 - NOR Flash
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 1801d9d..6c6b5d6 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -302,6 +302,19 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 2b816ce..5c0dc84 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -237,6 +237,18 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index e3830e5..33ac285 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -60,6 +60,7 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_NET
 
 #define CONFIG_SYS_PROMPT		"=> "
@@ -165,6 +166,20 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(2) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 5e86e4c..b5af493 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -57,6 +57,7 @@
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_LOADS
 #define CONFIG_CMD_EXT2
@@ -95,11 +96,6 @@
 #	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
 #	undef CONFIG_DM9000_DEBUG
 
-#	define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
-#	define CONFIG_IPADDR		10.82.121.249
-#	define CONFIG_NETMASK		255.255.252.0
-#	define CONFIG_SERVERIP		10.82.120.80
-#	define CONFIG_GATEWAYIP		10.82.123.254
 #	define CONFIG_OVERWRITE_ETHADDR_ONCE
 
 #	define CONFIG_EXTRA_ENV_SETTINGS		\
@@ -109,9 +105,9 @@
 		"u-boot=u-boot.bin\0"			\
 		"load=tftp ${loadaddr) ${u-boot}\0"	\
 		"upd=run load; run prog\0"		\
-		"prog=prot off 0 2ffff;"	\
-		"era 0 2ffff;"			\
-		"cp.b ${loadaddr} 0 ${filesize};"	\
+		"prog=prot off 0xff800000 0xff82ffff;"	\
+		"era 0xff800000 0xff82ffff;"		\
+		"cp.b ${loadaddr} 0xff800000 ${filesize};"	\
 		"save\0"				\
 		""
 #endif
@@ -231,6 +227,20 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(8) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /* Port configuration */
 #define CONFIG_SYS_FECI2C		0xF0
 
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index df6970c..206d115 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -64,6 +64,7 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_NET
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_LOADS
@@ -179,6 +180,20 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(2) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /* Port configuration */
 #define CONFIG_SYS_FECI2C		0xF0
 
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index 50b3ab2..798949c 100644
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -72,6 +72,7 @@
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_MII
@@ -229,6 +230,19 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /* Chip Select 0  : Boot Flash */
 #define CONFIG_SYS_CS0_BASE	0xFFE00000
 #define CONFIG_SYS_CS0_MASK	0x001F0001
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index f824158..f704bb3 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -74,6 +74,7 @@
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
@@ -211,6 +212,19 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index b380159..981670a 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -72,6 +72,7 @@
 /* Available command configuration */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
@@ -121,11 +122,6 @@
 #define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFF0)
 #define CONFIG_SYS_I2C_PINMUX_SET	(0x000F)
 
-#ifdef CONFIG_MCFFEC
-#define CONFIG_ETHADDR		00:06:3b:01:41:55
-#define CONFIG_ETH1ADDR		00:0e:0c:bc:e5:60
-#endif
-
 #define CONFIG_SYS_PROMPT		"-> "
 #define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
 
@@ -145,6 +141,23 @@
 #define CONFIG_SYS_MEMTEST_START	0x400
 #define CONFIG_SYS_MEMTEST_END		0x380000
 
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_NET_RETRY_COUNT	5
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* FEC_ENET */
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${uboot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off ffe00000 ffe3ffff;"	\
+	"era ffe00000 ffe3ffff;"		\
+	"cp.b ${loadaddr} ffe00000 ${filesize};"\
+	"save\0"				\
+	""
+
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CLK			150000000
 
@@ -208,6 +221,19 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 15590cf..6e0aa14 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -64,6 +64,7 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
@@ -209,6 +210,18 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DBWE | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 30855bd..d983a8f 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -69,6 +69,8 @@
 #	define CONFIG_MII_INIT		1
 #	define CONFIG_SYS_DISCOVER_PHY
 #	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_TX_ETH_BUFFER	8
+#	define CONFIG_SYS_FEC_BUF_USE_SRAM
 #	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #	define CONFIG_HAS_ETH1
 
@@ -166,7 +168,7 @@
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
 #define CONFIG_SYS_INIT_RAM_END		0x20000	/* End of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
@@ -180,7 +182,7 @@
 #define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
 #define CONFIG_SYS_SDRAM_CFG1		0x43711630
 #define CONFIG_SYS_SDRAM_CFG2		0x56670000
-#define CONFIG_SYS_SDRAM_CTRL		0xE1002000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
 #define CONFIG_SYS_SDRAM_EMOD		0x80010000
 #define CONFIG_SYS_SDRAM_MODE		0x00CD0000
 
@@ -231,6 +233,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 8180c05..159b178 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -237,6 +237,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 8652a80..af1988c 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -237,6 +237,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index a5acfd2..a80d330 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -309,6 +309,21 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE		16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+					 CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 7737284..5b4bba8 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -279,7 +279,7 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_END		0x8000	/* End of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL	0x221
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
@@ -408,6 +408,21 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE		16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+					 CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index 4534002..d007766 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -286,6 +286,22 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
+					 CF_CACR_IDCM)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_BCINVA | \
+					 CF_CACR_IEC | CF_CACR_ICINVA)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 971cb67..f23b8b0 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -272,6 +272,22 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
+					 CF_CACR_IDCM)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_BCINVA | \
+					 CF_CACR_IEC | CF_CACR_ICINVA)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h
index 518173a..e7429dd 100644
--- a/include/configs/METROBOX.h
+++ b/include/configs/METROBOX.h
@@ -194,6 +194,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C	      1		     /* I2C hardware support	*/
 #undef	CONFIG_SOFT_I2C			     /* I2C !bit-banged		*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED	      400000	     /* I2C speed 400kHz	*/
 #define CONFIG_SYS_I2C_SLAVE	      0x7F	     /* I2C slave address	*/
 #define CONFIG_SYS_I2C_NOPROBES      {0x69}	     /* Don't probe these addrs */
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 7ac9342..7e6484e 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -97,6 +97,7 @@
  ***************************************************************/
 
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 87901b3..da4313a 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -413,6 +413,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
 
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 9b81703..0c43b2b 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -284,6 +284,9 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
 
 #define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 1d2d659..8382e3c 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -177,7 +177,7 @@
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x0C    /* Reset altbank mask*/
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xC0    /* Reset altbank mask */
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
@@ -341,10 +341,8 @@
  * BAT0		2G	Cacheable, non-guarded
  * 0x0000_0000	2G	DDR
  */
-#define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CONFIG_SYS_IBAT0U	CONFIG_SYS_DBAT0U
+#define CONFIG_SYS_DBAT0L	(BATL_PP_RW)
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW)
 
 /*
  * BAT1		1G	Cache-inhibited, guarded
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 12a8f60..94e4d24 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -482,9 +482,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * BAT0		DDR
  */
 #define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CONFIG_SYS_IBAT0U	CONFIG_SYS_DBAT0U
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
 
 /*
  * BAT1		LBC (PIXIS/CF)
diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h
new file mode 100644
index 0000000..6492068
--- /dev/null
+++ b/include/configs/MVSMR.h
@@ -0,0 +1,295 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2010
+ * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <version.h>
+
+#define CONFIG_MPC5xxx	1
+#define CONFIG_MPC5200 	1
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
+
+#define BOOTFLAG_COLD		0x01
+#define BOOTFLAG_WARM		0x02
+
+#define CONFIG_MISC_INIT_R	1
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5
+#endif
+
+#define CONFIG_PSC_CONSOLE	1
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200,\
+						230400}
+
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#undef	CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_SYS_XLB_PIPELINING	1
+#define CONFIG_HIGH_BATS	1
+
+#define MV_CI			mvSMR
+#define MV_VCI			mvSMR
+#define MV_FPGA_DATA		0xff840000
+#define MV_FPGA_SIZE		0x1ff88
+#define MV_KERNEL_ADDR		0xfff00000
+#define MV_SCRIPT_ADDR		0xff806000
+#define MV_INITRD_ADDR		0xff880000
+#define MV_INITRD_LENGTH	0x00240000
+#define MV_SCRATCH_ADDR		0xffcc0000
+#define MV_SCRATCH_LENGTH	MV_INITRD_LENGTH
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define MV_KERNEL_ADDR_RAM	0x00100000
+#define MV_INITRD_ADDR_RAM	0x00400000
+
+/*
+ * Supported commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_RANDOM_DELAY
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_VENDOREX
+
+/*
+ * Autoboot
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR 	"abcdefg"
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTCOMMAND      "source ${script_addr}"
+#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs" \
+					" allocate=6M"
+
+#define XMK_STR(x)      #x
+#define MK_STR(x)       XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"console_nr=0\0"					\
+	"console=no\0"						\
+	"stdin=serial\0"					\
+	"stdout=serial\0"					\
+	"stderr=serial\0"					\
+	"fpga=0\0"						\
+	"fpgadata=" MK_STR(MV_FPGA_DATA) "\0"			\
+	"fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"		\
+	"mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0"		\
+	"mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"	\
+	"script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0"		\
+	"mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0"		\
+	"mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"	\
+	"mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0"	\
+	"mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0"		\
+	"mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0"	\
+	"mv_version=" U_BOOT_VERSION "\0"			\
+	"dhcp_client_id=" MK_STR(MV_CI) "\0"			\
+	"dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0"	\
+	"netretry=no\0"						\
+	"use_static_ipaddr=no\0"				\
+	"static_ipaddr=192.168.0.101\0"				\
+	"static_netmask=255.255.255.0\0"			\
+	"static_gateway=0.0.0.0\0"				\
+	"initrd_name=uInitrd.mvsmr-rfs\0"			\
+	"zcip=yes\0"						\
+	"netboot=no\0"						\
+	""
+
+#undef XMK_STR
+#undef MK_STR
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
+
+/*
+ * Flash configuration
+ */
+#undef 	CONFIG_FLASH_16BIT
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	50000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+#define CONFIG_SYS_LOWBOOT
+#define CONFIG_SYS_FLASH_BASE		TEXT_BASE
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#undef	CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_HAS_UID
+#define	CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#define CONFIG_ENV_OFFSET	0x8000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+
+/* used by linker script to wrap code around */
+#define CONFIG_SCRIPT_OFFSET	0x6000
+#define CONFIG_SCRIPT_SECT_SIZE	0x2000
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+						CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT		1
+#endif
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1
+#define CONFIG_SYS_I2C_MODULE	1
+#define CONFIG_SYS_I2C_SPEED	86000
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_NET_RETRY_COUNT 5
+
+#define CONFIG_MPC5xxx_FEC
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_NETDEV		eth0
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_PROMPT_HUSH_PS2 	"> "
+#undef 	CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"=> "
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE		1024
+#else
+#define CONFIG_SYS_CBSIZE		256
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x00800000
+#define CONFIG_SYS_MEMTEST_END		0x02f00000
+
+#define CONFIG_SYS_HZ			1000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x02000000
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 		0x00200000
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00050044
+
+#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047800
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_CS_BURST		0x000000f0
+#define CONFIG_SYS_CS_DEADCYCLE		0x33333303
+
+#define CONFIG_SYS_RESET_ADDRESS	0x00000100
+
+#undef FPGA_DEBUG
+#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA		CONFIG_SYS_XILINX_SPARTAN2
+#define CONFIG_FPGA_XILINX	1
+#define CONFIG_FPGA_SPARTAN2	1
+#define CONFIG_FPGA_COUNT	1
+
+#endif
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
index 860ec52..55471af 100644
--- a/include/configs/OCRTC.h
+++ b/include/configs/OCRTC.h
@@ -210,6 +210,7 @@
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h
index b2e2d41..1424713 100644
--- a/include/configs/ORSG.h
+++ b/include/configs/ORSG.h
@@ -208,6 +208,7 @@
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 405e6d5..a9b4004 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -286,6 +286,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
 
 #define CONFIG_SERIAL_MULTI	1 /* Enable both serial ports */
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 30a5a31..66be725 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -238,7 +238,9 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 
-#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#ifdef CONFIG_FSL_NGPIXIS
 #define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
 #ifdef CONFIG_PHYS_64BIT
 #define PIXIS_BASE_PHYS	0xfffdf0000ull
@@ -249,59 +251,11 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
 
-#define PIXIS_ID		0x0	/* Board ID at offset 0 */
-#define PIXIS_VER		0x1	/* Board version at offset 1 */
-#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
-#define PIXIS_CSR		0x3	/* PIXIS General control/status register */
-#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
-#define PIXIS_PWR		0x5	/* PIXIS Power status register */
-#define PIXIS_AUX		0x6	/* Auxiliary 1 register */
-#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
-#define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
-#define PIXIS_VCTL		0x10	/* VELA Control Register */
-#define PIXIS_VSTAT		0x11	/* VELA Status Register */
-#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
-#define PIXIS_VCORE0		0x14	/* VELA VCORE0 Register */
-#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
-#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
-#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
-#define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
-#define PIXIS_VSYSCLK0		0x19	/* VELA SYSCLK0 Register */
-#define PIXIS_VSYSCLK1		0x1A	/* VELA SYSCLK1 Register */
-#define PIXIS_VSYSCLK2		0x1B	/* VELA SYSCLK2 Register */
-#define PIXIS_VDDRCLK0		0x1C	/* VELA DDRCLK0 Register */
-#define PIXIS_VDDRCLK1		0x1D	/* VELA DDRCLK1 Register */
-#define PIXIS_VDDRCLK2		0x1E	/* VELA DDRCLK2 Register */
-
-#define PIXIS_VWATCH		0x24	/* Watchdog Register */
-#define PIXIS_LED		0x25	/* LED Register */
-
-#define PIXIS_SW(x)		0x20 + (x - 1) * 2
-#define PIXIS_EN(x)		0x21 + (x - 1) * 2
-#define PIXIS_SW7_LBMAP		0xc0	/* SW7 - cfg_lbmap */
-#define PIXIS_SW7_VBANK		0x30	/* SW7 - cfg_vbank */
-
-/* old pixis referenced names */
-#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
-#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
-#define PIXIS_VSPEED2_TSEC1SER	0x8
-#define PIXIS_VSPEED2_TSEC2SER	0x4
-#define PIXIS_VSPEED2_TSEC3SER	0x2
-#define PIXIS_VSPEED2_TSEC4SER	0x1
-#define PIXIS_VCFGEN1_TSEC1SER	0x20
-#define PIXIS_VCFGEN1_TSEC2SER	0x20
-#define PIXIS_VCFGEN1_TSEC3SER	0x20
-#define PIXIS_VCFGEN1_TSEC4SER	0x20
-#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER \
-					| PIXIS_VSPEED2_TSEC2SER \
-					| PIXIS_VSPEED2_TSEC3SER \
-					| PIXIS_VSPEED2_TSEC4SER)
-#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER \
-					| PIXIS_VCFGEN1_TSEC2SER \
-					| PIXIS_VCFGEN1_TSEC3SER \
-					| PIXIS_VCFGEN1_TSEC4SER)
+#define PIXIS_LBMAP_SWITCH	7
+#define PIXIS_LBMAP_MASK	0xf0
+#define PIXIS_LBMAP_SHIFT	4
+#define PIXIS_LBMAP_ALTBANK	0x20
+#endif
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 4e39799..0d443ea 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -204,6 +204,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h
index 831a60d..c60a9f7 100644
--- a/include/configs/PCI5441.h
+++ b/include/configs/PCI5441.h
@@ -92,7 +92,8 @@
 /*------------------------------------------------------------------------
  * CONSOLE
  *----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART		1	/* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
 #define CONFIG_SYS_NIOS_CONSOLE	0x00920820	/* JTAG UART base addr	*/
 #else
 #define CONFIG_SYS_NIOS_CONSOLE	0x009208a0	/* UART base addr	*/
@@ -113,14 +114,16 @@
  * TIMEBASE --
  *
  * The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
  *----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ			1000	/* Always 1000 */
 #define CONFIG_SYS_NIOS_TMRBASE	0x00920860	/* Tick timer base addr	*/
-#define CONFIG_SYS_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
-#define CONFIG_SYS_NIOS_TMRMS		10		/* 10 msec per tick	*/
-#define CONFIG_SYS_NIOS_TMRCNT	(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define	CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ		3	/* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+		(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
 
 
 /*
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 962b29e..3e57c0b 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -86,6 +86,7 @@
  * The Atmel EEPROM uses 16Bit addressing.
  ***************************************************************/
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h
index cf6f7a9..874c20b 100644
--- a/include/configs/PK1C20.h
+++ b/include/configs/PK1C20.h
@@ -94,7 +94,8 @@
 /*------------------------------------------------------------------------
  * CONSOLE
  *----------------------------------------------------------------------*/
-#if defined(CONFIG_CONSOLE_JTAG)
+#define CONFIG_ALTERA_UART		1	/* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
 #define CONFIG_SYS_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
 #else
 #define CONFIG_SYS_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
@@ -123,14 +124,16 @@
  * TIMEBASE --
  *
  * The high res timer defaults to 1 msec. Since it includes the period
- * registers, we can slow it down to 10 msec using TMRCNT. If the default
- * period is acceptable, TMRCNT can be left undefined.
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
  *----------------------------------------------------------------------*/
+#define CONFIG_SYS_HZ			1000	/* Always 1000 */
 #define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
-#define CONFIG_SYS_NIOS_TMRMS		10		/* 10 msec per tick	*/
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
+#define CONFIG_SYS_NIOS_TMRIRQ		3	/* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period */
+#define CONFIG_SYS_NIOS_TMRCNT \
+		(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
 
 /*------------------------------------------------------------------------
  * STATUS LED -- Provides a simple blinking led. For Nios2 each board
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 3d59454..f917eb5 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -278,6 +278,7 @@
  * I2C EEPROM (24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index f9687d2..22de207 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -50,7 +50,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 
-#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
 /*
  * PCI Mapping:
  * 0x40000000 - 0x4fffffff - PCI Memory
@@ -75,7 +74,6 @@
 #define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #undef  CONFIG_NS8382X
 
-#endif
 
 /* Partitions */
 #define CONFIG_DOS_PARTITION
@@ -111,9 +109,7 @@
 #define CONFIG_CMD_SNTP
 #define CONFIG_CMD_USB
 
-#if defined(CONFIG_MPC5200)
 #define CONFIG_CMD_PCI
-#endif
 
 
 /*
@@ -147,12 +143,10 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#if defined(CONFIG_MPC5200)
 /*
  * IPB Bus clocking configuration.
  */
 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-#endif
 /*
  * I2C configuration
  */
@@ -301,13 +295,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #if defined(CONFIG_BOOT_ROM)
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_BOOTROM_BASE
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index 87ea7b6..00a12fb 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -235,6 +235,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		100000 /* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
index 7198632..2c048dd 100644
--- a/include/configs/PMC405DE.h
+++ b/include/configs/PMC405DE.h
@@ -215,6 +215,7 @@
  * I2C EEPROM (24W16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000 /* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 89799af..c2fb56c 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -226,6 +226,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support    */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged               */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address  */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 8e9d928..44f03dc 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -414,6 +414,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index 25f3a26..b69f015 100644
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -252,6 +252,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index 3438aba..6da18eb 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -430,13 +430,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 2154c78..107bff1 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -633,13 +633,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
index 1daa574..7510ab1 100644
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -41,6 +41,7 @@
  */
 
 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* (more precisely a MPC5200 CPU) */
 #define CONFIG_TOTAL5200	1	/* ... on Total5200 board */
 
 #define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
@@ -73,7 +74,6 @@
 #define CONFIG_SPLASH_SCREEN
 
 
-#ifdef CONFIG_MPC5200	/* MGT5100 PCI is not supported yet. */
 /*
  * PCI Mapping:
  * 0x40000000 - 0x4fffffff - PCI Memory
@@ -98,12 +98,6 @@
 #define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X		1
 
-#else	/* MGT5100 */
-
-#define CONFIG_MII		1
-
-#endif
-
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -127,9 +121,7 @@
  */
 #include <config_cmd_default.h>
 
-#if defined(CONFIG_MPC5200)
-    #define CONFIG_CMD_PCI
-#endif
+#define CONFIG_CMD_PCI
 
 #define CONFIG_CMD_BMP
 #define CONFIG_CMD_EEPROM
@@ -176,12 +168,10 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#if defined(CONFIG_MPC5200)
 /*
  * IPB Bus clocking configuration.
  */
 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-#endif
 
 /*
  * I2C configuration
@@ -326,17 +316,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
-
-#if defined (CONFIG_MGT5100)
-#   define CONFIG_BOARD_EARLY_INIT_R	/* switch from CS_BOOT to CS0 */
-#endif
 
 #if CONFIG_TOTAL5200_REV==1
 #   define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index 38a1d0d..9c91fcc 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -277,6 +277,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index 4717869..871e4c3 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -203,6 +203,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index c017915..f06bfe5 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -273,6 +273,7 @@
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
index 1d4ad13..be8c9f8 100644
--- a/include/configs/W7OLMG.h
+++ b/include/configs/W7OLMG.h
@@ -280,6 +280,7 @@
  * I2C EEPROM (ATMEL 24C04N)
  */
 #define CONFIG_HARD_I2C		1		/* Hardware assisted I2C	*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index 5c281a1..be9ac62 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -241,6 +241,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/XPEDITE1000.h b/include/configs/XPEDITE1000.h
index 658e947..cf39aea 100644
--- a/include/configs/XPEDITE1000.h
+++ b/include/configs/XPEDITE1000.h
@@ -141,6 +141,7 @@ extern void out32(unsigned int, unsigned long);
  * I2C
  */
 #define CONFIG_HARD_I2C			1	/* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7f
 #define CONFIG_I2C_MULTI_BUS
diff --git a/include/configs/aev.h b/include/configs/aev.h
index 2b4826d..98958a6 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -362,13 +362,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index 0fed9ad..ee0c14d 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -118,6 +118,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs	*/
@@ -235,11 +236,13 @@
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_FPGA
 #define CONFIG_CMD_I2C
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
 #undef CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 8cd97b8..13a941e 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -40,6 +40,7 @@
  * I2C
  */
 #define CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
diff --git a/include/configs/aria.h b/include/configs/aria.h
index f89fc57..06763c5 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -190,7 +190,7 @@
 
 /*
  * Backward compatible definitions,
- * so we do not have to change cpu/mpc512x/fixed_sdram.c
+ * so we do not have to change arch/ppc/cpu/mpc512x/fixed_sdram.c
  */
 #define	CONFIG_SYS_DDRCMD_EM2		(CONFIG_SYS_MICRON_EMR2)
 #define CONFIG_SYS_DDRCMD_EM3		(CONFIG_SYS_MICRON_EMR3)
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
new file mode 100644
index 0000000..7c8281c
--- /dev/null
+++ b/include/configs/astro_mcf5373l.h
@@ -0,0 +1,400 @@
+/*
+ * Configuration settings for the Sentec Cobra Board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * configuration for ASTRO "Urmel" board.
+ * Originating from Cobra5272 configuration, messed up by
+ * Wolfgang Wegner <w.wegner@astro-kom.de>
+ * Please do not bother the original author with bug reports
+ * concerning this file.
+ */
+
+#ifndef _CONFIG_ASTRO_MCF5373L_H
+#define _CONFIG_ASTRO_MCF5373L_H
+
+/*
+ * set the card type to actually compile for; either of
+ * the possibilities listed below has to be used!
+ */
+#define CONFIG_ASTRO_V532	1
+
+#if CONFIG_ASTRO_V532
+#define ASTRO_ID	0xF8
+#elif CONFIG_ASTRO_V512
+#define ASTRO_ID	0xFA
+#elif CONFIG_ASTRO_TWIN7S2
+#define ASTRO_ID	0xF9
+#elif CONFIG_ASTRO_V912
+#define ASTRO_ID	0xFC
+#elif CONFIG_ASTRO_COFDMDUOS2
+#define ASTRO_ID	0xFB
+#else
+#error No card type defined!
+#endif
+
+/*
+ * Define processor
+ * possible values for Urmel board: only Coldfire M5373 processor supported
+ * (please do not change)
+ */
+
+/* it seems not clear yet which processor defines we should use */
+#define CONFIG_MCF537x			/* define processor family */
+#define CONFIG_MCF532x			/* define processor family */
+#define CONFIG_M5373			/* define processor type */
+#define CONFIG_ASTRO5373L		/* define board type */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+/*
+ * CONFIG_MK_RAM defines if u-boot is loaded via BDM (or started from
+ * a different bootloader that has already performed RAM setup) or
+ * started directly from flash, which is the regular case for production
+ * boards.
+ */
+#ifdef CONFIG_MK_RAM
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_TEXT_BASE		0x40020000
+#define ENABLE_JFFS	0
+#else
+#define CONFIG_TEXT_BASE		0x00000000
+#define ENABLE_JFFS	1
+#endif
+
+/* Define which commmands should be available at u-boot command prompt */
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_XIMG
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#if ENABLE_JFFS
+#define CONFIG_CMD_JFFS2
+#endif
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C			/* I2C with hw support */
+#undef CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+/*
+ * Defines processor clock - important for correct timings concerning serial
+ * interface etc.
+ * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
+ */
+
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_CLK			80000000
+#define CONFIG_SYS_CPU_CLK		(CONFIG_SYS_CLK * 3)
+#define CONFIG_SYS_SDRAM_SIZE		32		/* SDRAM size in MB */
+
+#define CONFIG_SYS_CORE_SRAM_SIZE	0x8000
+#define CONFIG_SYS_CORE_SRAM		0x80000000
+
+#define CONFIG_SYS_UNIFY_CACHE
+
+/*
+ * Define baudrate for UART1 (console output, tftp, ...)
+ * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
+ * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected
+ * in u-boot command interface
+ */
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(2)
+#define CONFIG_SYS_UART2_ALT3_GPIO
+
+/*
+ * Watchdog configuration; Watchdog is disabled for running from RAM
+ * and set to highest possible value else. Beware there is no check
+ * in the watchdog code to validate the timeout value set here!
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 3355	/* timeout in milliseconds */
+#endif
+
+/*
+ * Configuration for environment
+ * Environment is located in the last sector of the flash
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_ENV_OFFSET		0x1FF8000
+#define CONFIG_ENV_SECT_SIZE		0x8000
+#define CONFIG_ENV_IS_IN_FLASH		1
+#else
+/*
+ * environment in RAM - This is used to use a single PC-based application
+ * to load an image, load U-Boot, load an environment and then start U-Boot
+ * to execute the commands from the environment. Feedback is done via setting
+ * and reading memory locations.
+ */
+#define CONFIG_ENV_ADDR		0x40060000
+#define CONFIG_ENV_SECT_SIZE	0x8000
+#define CONFIG_ENV_IS_IN_FLASH	1
+#endif
+
+/* here we put our FPGA configuration... */
+#define CONFIG_MISC_INIT_R	1
+
+/* Define user parameters that have to be customized most likely */
+
+/* AUTOBOOT settings - booting images automatically by u-boot after power on */
+
+/*
+ * used for autoboot, delay in seconds u-boot will wait before starting
+ * defined (auto-)boot command, setting to -1 disables delay, setting to
+ * 0 will too prevent access to u-boot command interface: u-boot then has
+ * to be reflashed
+ * beware - watchdog is not serviced during autoboot delay time!
+ */
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_BOOTDELAY	1
+#else
+#define CONFIG_BOOTDELAY	1
+#endif
+
+/*
+ * The following settings will be contained in the environment block ; if you
+ * want to use a neutral environment all those settings can be manually set in
+ * u-boot: 'set' command
+ */
+
+#define _QUOTEME(x)	#x
+#define QUOTEME(x)	_QUOTEME(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS			\
+	"loaderversion=11\0"				\
+	"card_id="QUOTEME(ASTRO_ID)"\0"			\
+	"alterafile=0\0"				\
+	"xilinxfile=0\0"				\
+	"xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\
+		"fpga load 0 0x41000000 $filesize\0" \
+	"alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\
+		"fpga load 1 0x41000000 $filesize\0" \
+	"env_default=1\0"				\
+	"env_check=if test $env_default -eq 1;"\
+		" then setenv env_default 0;saveenv;fi\0"
+
+/*
+ * "update" is a non-standard command that has to be supplied
+ * by external update.c; This is not included in mainline because
+ * it needs non-blocking CFI routines.
+ */
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_BOOTCOMMAND	""	/* no autoboot in this case */
+#else
+#if CONFIG_ASTRO_V532
+#define CONFIG_BOOTCOMMAND	"protect off 0x80000 0x1ffffff;run env_check;"\
+				"run xilinxload&&run alteraload&&bootm 0x80000;"\
+				"update;reset"
+#else
+#define CONFIG_BOOTCOMMAND	"protect off 0x80000 0x1ffffff;run env_check;"\
+				"run xilinxload&&bootm 0x80000;update;reset"
+#endif
+#endif
+
+/* default bootargs that are considered during boot */
+#define CONFIG_BOOTARGS		" console=ttyS2,115200 rootfstype=romfs"\
+				" loaderversion=$loaderversion"
+
+#define CONFIG_SYS_PROMPT	"URMEL > "
+
+/* default RAM address for user programs */
+#define CONFIG_SYS_LOAD_ADDR	0x20000
+
+#define CONFIG_SYS_LONGHELP
+
+#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024
+#else
+#define CONFIG_SYS_CBSIZE		256
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_FPGA_COUNT	1
+#define CONFIG_FPGA
+#define	CONFIG_FPGA_XILINX
+#define	CONFIG_FPGA_SPARTAN3
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_WAIT		1000
+
+/* End of user parameters to be customized */
+
+/* Defines memory range for test */
+
+#define CONFIG_SYS_MEMTEST_START	0x40020000
+#define CONFIG_SYS_MEMTEST_END		0x41ffffff
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/* Base register address */
+
+#define CONFIG_SYS_MBAR		0xFC000000	/* Register Base Addrs */
+
+/* System Conf. Reg. & System Protection Reg. */
+
+#define CONFIG_SYS_SCR		0x0003;
+#define CONFIG_SYS_SPR		0xffff;
+
+/*
+ * Definitions for initial stack pointer and data area (in internal SRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_END		0x8000
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+
+/*
+ * Chipselect bank definitions
+ *
+ * CS0 - Flash 32MB (first 16MB)
+ * CS1 - Flash 32MB (second half)
+ * CS2 - FPGA
+ * CS3 - FPGA
+ * CS4 - unused
+ * CS5 - unused
+ */
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x00ff0001
+#define CONFIG_SYS_CS0_CTRL		0x00001fc0
+
+#define CONFIG_SYS_CS1_BASE		0x01000000
+#define CONFIG_SYS_CS1_MASK		0x00ff0001
+#define CONFIG_SYS_CS1_CTRL		0x00001fc0
+
+#define CONFIG_SYS_CS2_BASE		0x20000000
+#define CONFIG_SYS_CS2_MASK		0x00ff0001
+#define CONFIG_SYS_CS2_CTRL		0x0000fec0
+
+#define CONFIG_SYS_CS3_BASE		0x21000000
+#define CONFIG_SYS_CS3_MASK		0x00ff0001
+#define CONFIG_SYS_CS3_CTRL		0x0000fec0
+
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+
+#ifdef	CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_TEXT_BASE
+#else
+/* This is mainly used during relocation in start.S */
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64 * 1024)
+/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + \
+						(CONFIG_SYS_SDRAM_SIZE << 20))
+
+/* FLASH organization */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	259
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define CONFIG_SYS_FLASH_SIZE		0x2000000
+#define CONFIG_SYS_FLASH_PROTECTION	1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_FLASH_CFI_NONBLOCK	1
+
+#if ENABLE_JFFS
+/* JFFS Partition offset set */
+#define CONFIG_SYS_JFFS2_FIRST_BANK    0
+#define CONFIG_SYS_JFFS2_NUM_BANKS     1
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR  0x40
+#endif
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
+#endif	/* _CONFIG_ASTRO_MCF5373L_H */
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 083c030..80c4884 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -126,11 +126,11 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	cpu/blackfin/traps.o		(.text .text.*); \
-	cpu/blackfin/interrupt.o	(.text .text.*); \
-	cpu/blackfin/serial.o		(.text .text.*); \
+	arch/blackfin/cpu/traps.o		(.text .text.*); \
+	arch/blackfin/cpu/interrupt.o	(.text .text.*); \
+	arch/blackfin/cpu/serial.o		(.text .text.*); \
 	common/dlmalloc.o		(.text .text.*); \
-	lib_generic/crc32.o		(.text .text.*); \
+	lib/crc32.o		(.text .text.*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o		(.text .text.*);
 #endif
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
index 6627a04..cf40d06 100644
--- a/include/configs/bf537-pnav.h
+++ b/include/configs/bf537-pnav.h
@@ -112,11 +112,11 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	cpu/blackfin/traps.o		(.text .text.*); \
-	cpu/blackfin/interrupt.o	(.text .text.*); \
-	cpu/blackfin/serial.o		(.text .text.*); \
+	arch/blackfin/cpu/traps.o		(.text .text.*); \
+	arch/blackfin/cpu/interrupt.o	(.text .text.*); \
+	arch/blackfin/cpu/serial.o		(.text .text.*); \
 	common/dlmalloc.o		(.text .text.*); \
-	lib_generic/crc32.o		(.text .text.*); \
+	lib/crc32.o		(.text .text.*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o		(.text .text.*);
 #endif
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index de2add7..92ceb38 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -122,11 +122,11 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	cpu/blackfin/traps.o		(.text .text.*); \
-	cpu/blackfin/interrupt.o	(.text .text.*); \
-	cpu/blackfin/serial.o		(.text .text.*); \
+	arch/blackfin/cpu/traps.o		(.text .text.*); \
+	arch/blackfin/cpu/interrupt.o	(.text .text.*); \
+	arch/blackfin/cpu/serial.o		(.text .text.*); \
 	common/dlmalloc.o		(.text .text.*); \
-	lib_generic/crc32.o		(.text .text.*); \
+	lib/crc32.o		(.text .text.*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o		(.text .text.*);
 #endif
@@ -277,6 +277,15 @@
 #define FLASH_END_POST_BLOCK	71	/* Should < = 71 */
 #endif
 
+/* These are for board tests */
+#if 0
+#define CONFIG_BOOTCOMMAND       "bootldr 0x203f0100"
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT \
+	"autoboot in %d seconds: press space to stop\n", bootdelay
+#define CONFIG_AUTOBOOT_STOP_STR " "
+#endif
+
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
index 4ea2300..59e0565 100644
--- a/include/configs/bf538f-ezkit.h
+++ b/include/configs/bf538f-ezkit.h
@@ -119,11 +119,11 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	cpu/blackfin/traps.o		(.text .text.*); \
-	cpu/blackfin/interrupt.o	(.text .text.*); \
-	cpu/blackfin/serial.o		(.text .text.*); \
+	arch/blackfin/cpu/traps.o		(.text .text.*); \
+	arch/blackfin/cpu/interrupt.o	(.text .text.*); \
+	arch/blackfin/cpu/serial.o		(.text .text.*); \
 	common/dlmalloc.o		(.text .text.*); \
-	lib_generic/crc32.o		(.text .text.*); \
+	lib/crc32.o		(.text .text.*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o		(.text .text.*);
 #endif
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 8ab38bb..1e3fdef 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -96,12 +96,12 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	cpu/blackfin/traps.o		(.text .text.*); \
-	cpu/blackfin/interrupt.o	(.text .text.*); \
-	cpu/blackfin/serial.o		(.text .text.*); \
+	arch/blackfin/cpu/traps.o		(.text .text.*); \
+	arch/blackfin/cpu/interrupt.o	(.text .text.*); \
+	arch/blackfin/cpu/serial.o		(.text .text.*); \
 	common/dlmalloc.o		(.text .text.*); \
-	lib_generic/crc32.o		(.text .text.*); \
-	lib_generic/zlib.o		(.text .text.*); \
+	lib/crc32.o		(.text .text.*); \
+	lib/zlib.o		(.text .text.*); \
 	board/bf561-ezkit/bf561-ezkit.o	(.text .text.*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o		(.text .text.*);
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 0d68eba..8d0bc12 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -104,11 +104,11 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	cpu/blackfin/traps.o		(.text .text.*); \
-	cpu/blackfin/interrupt.o	(.text .text.*); \
-	cpu/blackfin/serial.o		(.text .text.*); \
+	arch/blackfin/cpu/traps.o		(.text .text.*); \
+	arch/blackfin/cpu/interrupt.o	(.text .text.*); \
+	arch/blackfin/cpu/serial.o		(.text .text.*); \
 	common/dlmalloc.o		(.text .text.*); \
-	lib_generic/crc32.o		(.text .text.*); \
+	lib/crc32.o		(.text .text.*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o		(.text .text.*);
 #endif
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index c1179b0..bbea3ab 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -105,11 +105,11 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	cpu/blackfin/traps.o		(.text .text.*); \
-	cpu/blackfin/interrupt.o	(.text .text.*); \
-	cpu/blackfin/serial.o		(.text .text.*); \
+	arch/blackfin/cpu/traps.o		(.text .text.*); \
+	arch/blackfin/cpu/interrupt.o	(.text .text.*); \
+	arch/blackfin/cpu/serial.o		(.text .text.*); \
 	common/dlmalloc.o		(.text .text.*); \
-	lib_generic/crc32.o		(.text .text.*); \
+	lib/crc32.o		(.text .text.*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o		(.text .text.*);
 #endif
diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h
index 1741ed4..c60401c 100644
--- a/include/configs/cm-bf561.h
+++ b/include/configs/cm-bf561.h
@@ -63,14 +63,10 @@
  * Network Settings
  */
 #define ADI_CMDS_NETWORK	1
-/* The next 2 lines are for use with DEV-BF5xx */
 #define CONFIG_NET_MULTI
-#define CONFIG_SMC91111	1
-#define CONFIG_SMC91111_BASE	0x28000300
-/* The next 3 lines are for use with EXT-BF5xx-USB-ETH2 */
-/* #define CONFIG_DRIVER_SMC911X 1 */
-/* #define CONFIG_DRIVER_SMC911X_BASE 0x24080000 /! AMS1 */
-/* #define CONFIG_DRIVER_SMC911X_32_BIT 1 */
+#define CONFIG_SMC911X		1
+#define CONFIG_SMC911X_BASE	0x24008000 /* AMS1 */
+#define CONFIG_SMC911X_16_BIT
 #define CONFIG_HOSTNAME		cm-bf561
 /* Uncomment next line to use fixed MAC address */
 /* #define CONFIG_ETHADDR	02:80:ad:20:31:cf */
@@ -94,6 +90,7 @@
 #define CONFIG_ENV_OFFSET	0x20000
 #define CONFIG_ENV_SECT_SIZE	0x20000
 #define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 
 
 /*
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 1c3ea23..330e3ac 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -331,6 +331,19 @@ from which user programs will be started */
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  *
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
index 52df16a..f7290d6 100644
--- a/include/configs/cpci5200.h
+++ b/include/configs/cpci5200.h
@@ -59,7 +59,6 @@
 #define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#ifdef CONFIG_MPC5200		/* MPC5100 PCI is not supported yet. */
 /*
  * PCI Mapping:
  * 0x40000000 - 0x4fffffff - PCI Memory
@@ -90,8 +89,6 @@
 #define CONFIG_NS8382X		1
 #endif
 
-#endif
-
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -169,8 +166,6 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
 
-#if defined(CONFIG_MPC5200)
-
 #define CONFIG_RTC_M48T35A	1	/* ST Electronics M48 timekeeper */
 #define CONFIG_SYS_NVRAM_BASE_ADDR	0xfd010000
 #define CONFIG_SYS_NVRAM_SIZE		32*1024
@@ -179,7 +174,6 @@
  * IPB Bus clocking configuration.
  */
 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-#endif
 /*
  * I2C configuration
  */
@@ -303,13 +297,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/csb272.h b/include/configs/csb272.h
index aed6f50..9ded330 100644
--- a/include/configs/csb272.h
+++ b/include/configs/csb272.h
@@ -171,6 +171,7 @@
  *
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed			*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address		*/
 
diff --git a/include/configs/csb472.h b/include/configs/csb472.h
index 24b961f..71eb083 100644
--- a/include/configs/csb472.h
+++ b/include/configs/csb472.h
@@ -170,6 +170,7 @@
  *
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed			*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address		*/
 
diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h
index 4be28b2..44669ea 100644
--- a/include/configs/galaxy5200.h
+++ b/include/configs/galaxy5200.h
@@ -141,7 +141,7 @@
 
 #define CONFIG_SYS_FLASH_BASE		0xfe000000
 /*
- * The flash size is autoconfigured, but cpu/mpc5xxx/cpu_init.c needs this
+ * The flash size is autoconfigured, but arch/ppc/cpu/mpc5xxx/cpu_init.c needs this
  * variable defined
  */
 #define CONFIG_SYS_FLASH_SIZE		0x02000000
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index a81527e..f9cdcbc 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -261,13 +261,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h
index 7c9f71e..2eef5ef 100644
--- a/include/configs/ibf-dsp561.h
+++ b/include/configs/ibf-dsp561.h
@@ -84,12 +84,12 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	cpu/blackfin/traps.o		(.text .text.*); \
-	cpu/blackfin/interrupt.o	(.text .text.*); \
-	cpu/blackfin/serial.o		(.text .text.*); \
+	arch/blackfin/cpu/traps.o		(.text .text.*); \
+	arch/blackfin/cpu/interrupt.o	(.text .text.*); \
+	arch/blackfin/cpu/serial.o		(.text .text.*); \
 	common/dlmalloc.o		(.text .text.*); \
-	lib_generic/crc32.o		(.text .text.*); \
-	lib_generic/zlib.o		(.text .text.*); \
+	lib/crc32.o		(.text .text.*); \
+	lib/zlib.o		(.text .text.*); \
 	board/ibf-dsp561/ibf-dsp561.o	(.text .text.*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o		(.text .text.*);
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
index 841affb..61e3bad 100644
--- a/include/configs/idmr.h
+++ b/include/configs/idmr.h
@@ -224,6 +224,19 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /* Port configuration */
 #define CONFIG_SYS_FECI2C		0xF0
 
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
new file mode 100644
index 0000000..1da8602
--- /dev/null
+++ b/include/configs/imx27lite-common.h
@@ -0,0 +1,237 @@
+/*
+ * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
+ *
+ * based on:
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMX27LITE_COMMON_CONFIG_H
+#define __IMX27LITE_COMMON_CONFIG_H
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
+#define CONFIG_MX27
+#define CONFIG_MX27_CLK32	32768		/* OSC32K frequency */
+#define CONFIG_SYS_HZ		1000
+
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Lowlevel configuration
+ */
+#define SDRAM_ESDCFG_REGISTER_VAL(cas)	\
+		(ESDCFG_TRC(10) |	\
+		ESDCFG_TRCD(3) |	\
+		ESDCFG_TCAS(cas) |	\
+		ESDCFG_TRRD(1) |	\
+		ESDCFG_TRAS(5) |	\
+		ESDCFG_TWR |		\
+		ESDCFG_TMRD(2) |	\
+		ESDCFG_TRP(2) |		\
+		ESDCFG_TXP(3))
+
+#define SDRAM_ESDCTL_REGISTER_VAL	\
+		(ESDCTL_PRCT(0) |	\
+		 ESDCTL_BL |		\
+		 ESDCTL_PWDT(0) |	\
+		 ESDCTL_SREFR(3) |	\
+		 ESDCTL_DSIZ_32 |	\
+		 ESDCTL_COL10 |		\
+		 ESDCTL_ROW13 |		\
+		 ESDCTL_SDE)
+
+#define SDRAM_ALL_VAL		0xf00
+
+#define SDRAM_MODE_REGISTER_VAL	0x33	/* BL: 8, CAS: 3 */
+#define SDRAM_EXT_MODE_REGISTER_VAL	0x1000000
+
+#define MPCTL0_VAL	0x1ef15d5
+
+#define SPCTL0_VAL	0x043a1c09
+
+#define CSCR_VAL	0x33f08107
+
+#define PCDR0_VAL	0x120470c3
+#define PCDR1_VAL	0x03030303
+#define PCCR0_VAL	0xffffffff
+#define PCCR1_VAL	0xfffffffc
+
+#define AIPI1_PSR0_VAL	0x20040304
+#define AIPI1_PSR1_VAL	0xdffbfcfb
+#define AIPI2_PSR0_VAL	0x07ffc200
+#define AIPI2_PSR1_VAL	0xffffffff
+
+/*
+ * Memory Info
+ */
+/* malloc() len */
+#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 512 * 1024)
+/* reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+/* memtest start address */
+#define CONFIG_SYS_MEMTEST_START	0xA0000000
+#define CONFIG_SYS_MEMTEST_END		0xA1000000	/* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE	(256 * 1024)	/* regular stack */
+#define PHYS_SDRAM_1		0xA0000000	/* DDR Start */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX27_UART1
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Flash & Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_PROTECTION		1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of flash banks */
+/* CS2 Base address */
+#define PHYS_FLASH_1			0xc0000000
+/* Flash Base for U-Boot */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT	(PHYS_FLASH_SIZE / \
+		CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256KiB */
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0x1f
+#define CONFIG_MII
+#define CONFIG_NET_MULTI
+
+/*
+ * MTD
+ */
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_DEVICE
+
+/*
+ * NAND
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE	0xd8000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0xd8000000
+#define CONFIG_JFFS2_NAND
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXC_MMC
+#define CONFIG_DOS_PARTITION
+
+/*
+ * MTD partitions
+ */
+#define CONFIG_CMD_MTDPARTS
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
+/* Print buffer sz */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+		sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_LOADADDR		0xa0800000	/* loadaddr env var */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc0,${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"			\
+	"kernel_addr_r=a0800000\0"					\
+	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
+	"rootpath=/opt/eldk-4.2-arm/arm\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm\0"						\
+	"bootcmd=run net_nfs\0"					\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)		\
+		" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};cp.b ${fileaddr} "			\
+		xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"		\
+	"upd=run load update\0"						\
+	"mtdids=" MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+
+#endif /* __IMX27LITE_COMMON_CONFIG_H */
diff --git a/include/configs/imx27lite.h b/include/configs/imx27lite.h
index ee749ec..72f6e80 100644
--- a/include/configs/imx27lite.h
+++ b/include/configs/imx27lite.h
@@ -20,158 +20,31 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+/* include common defines/options for all imx27lite related boards */
+#include "imx27lite-common.h"
 /*
  * SoC Configuration
  */
-#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
-#define CONFIG_MX27
 #define CONFIG_IMX27LITE
-#define CONFIG_MX27_CLK32	32768		/* OSC32K frequency */
-#define CONFIG_SYS_HZ		1000
-
-#define CONFIG_DISPLAY_CPUINFO
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-
-/*
- * Lowlevel configuration
- */
-#define SDRAM_ESDCFG_REGISTER_VAL(cas)	\
-		(ESDCFG_TRC(10) |	\
-		ESDCFG_TRCD(3) |	\
-		ESDCFG_TCAS(cas) |	\
-		ESDCFG_TRRD(1) |	\
-		ESDCFG_TRAS(5) |	\
-		ESDCFG_TWR |		\
-		ESDCFG_TMRD(2) |	\
-		ESDCFG_TRP(2) |		\
-		ESDCFG_TXP(3))
-
-#define SDRAM_ESDCTL_REGISTER_VAL	\
-		(ESDCTL_PRCT(0) |	\
-		 ESDCTL_BL |		\
-		 ESDCTL_PWDT(0) |	\
-		 ESDCTL_SREFR(3) |	\
-		 ESDCTL_DSIZ_32 |	\
-		 ESDCTL_COL10 |		\
-		 ESDCTL_ROW13 |		\
-		 ESDCTL_SDE)
-
-#define SDRAM_ALL_VAL		0xf00
-
-#define SDRAM_MODE_REGISTER_VAL	0x33	/* BL: 8, CAS: 3 */
-#define SDRAM_EXT_MODE_REGISTER_VAL	0x1000000
-
-#define MPCTL0_VAL	0x1ef15d5
-
-#define SPCTL0_VAL	0x043a1c09
-
-#define CSCR_VAL	0x33f08107
-
-#define PCDR0_VAL	0x120470c3
-#define PCDR1_VAL	0x03030303
-#define PCCR0_VAL	0xffffffff
-#define PCCR1_VAL	0xfffffffc
-
-#define AIPI1_PSR0_VAL	0x20040304
-#define AIPI1_PSR1_VAL	0xdffbfcfb
-#define AIPI2_PSR0_VAL	0x07ffc200
-#define AIPI2_PSR1_VAL	0xffffffff
-
-/*
- * Memory Info
- */
-/* malloc() len */
-#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 512 * 1024)
-/* reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-/* memtest start address */
-#define CONFIG_SYS_MEMTEST_START	0xA0000000
-#define CONFIG_SYS_MEMTEST_END		0xA1000000	/* 16MB RAM test */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define CONFIG_STACKSIZE	(256 * 1024)	/* regular stack */
-#define PHYS_SDRAM_1		0xA0000000	/* DDR Start */
-#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
-
-/*
- * Serial Driver info
- */
-#define CONFIG_MXC_UART
-#define CONFIG_SYS_MX27_UART1
-#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
-#define CONFIG_BAUDRATE		115200		/* Default baud rate */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_HOSTNAME		imx27
+#define CONFIG_BOARDNAME	"LogicPD imx27lite\n"
 
 /*
  * Flash & Environment
  */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-/* Use buffered writes (~10x faster) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
-/* Use hardware sector protection */
-#define CONFIG_SYS_FLASH_PROTECTION		1
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of flash banks */
 #define CONFIG_SYS_FLASH_SECT_SZ	0x2000	/* 8KB sect size Intel Flash */
-/* end of flash */
 #define CONFIG_ENV_OFFSET		(PHYS_FLASH_SIZE - 0x20000)
-/* CS2 Base address */
-#define PHYS_FLASH_1			0xc0000000
-/* Flash Base for U-Boot */
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-/* Flash size 2MB */
 #define PHYS_FLASH_SIZE			0x200000
-#define CONFIG_SYS_MAX_FLASH_SECT	(PHYS_FLASH_SIZE / \
-		CONFIG_SYS_FLASH_SECT_SZ)
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256KiB */
 #define CONFIG_ENV_SECT_SIZE		0x10000		/* Env sector Size */
-#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
-
-/*
- * Ethernet
- */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_MXC_PHYADDR		0x1f
-#define CONFIG_MII
-#define CONFIG_NET_MULTI
-
-/*
- * MTD
- */
-#define CONFIG_FLASH_CFI_MTD
-#define CONFIG_MTD_DEVICE
-
-/*
- * NAND
- */
-#define CONFIG_NAND_MXC
-#define CONFIG_MXC_NAND_REGS_BASE	0xd8000000
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		0xd8000000
-#define CONFIG_JFFS2_NAND
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 
 /*
  * SD/MMC
  */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MXC_MMC
 #define CONFIG_MXC_MCI_REGS_BASE	0x10014000
-#define CONFIG_DOS_PARTITION
 
 /*
  * MTD partitions
  */
-#define CONFIG_CMD_MTDPARTS
 #define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=mxc_nand.0"
 #define MTDPARTS_DEFAULT			\
 	"mtdparts="				\
@@ -186,69 +59,4 @@
 			"22m(rootfs),"		\
 			"-(userfs)"
 
-/*
- * U-Boot general configuration
- */
-#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
-/* Print buffer sz */
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
-		sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_LONGHELP
-
-/*
- * U-Boot commands
- */
-#include <config_cmd_default.h>
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-
-#define CONFIG_BOOTDELAY	5
-
-#define CONFIG_LOADADDR		0xa0800000	/* loadaddr env var */
-#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-
-#define xstr(s)	str(s)
-#define str(s)	#s
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs}"				\
-		" console=ttymxc0,${baudrate}\0"			\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"addmisc=setenv bootargs ${bootargs}\0"				\
-	"u-boot=imx27/u-boot.bin\0"					\
-	"kernel_addr_r=a0800000\0"					\
-	"hostname=imx27\0"						\
-	"bootfile=imx27/uImage\0"					\
-	"rootpath=/opt/eldk-4.2-arm/arm\0"				\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"run nfsargs addip addtty addmtd addmisc;"		\
-		"bootm\0"						\
-	"bootcmd=run net_nfs\0"					\
-	"load=tftp ${loadaddr} ${u-boot}\0"				\
-	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)		\
-		" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)	\
-		" +${filesize};cp.b ${fileaddr} "			\
-		xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"		\
-	"upd=run load update\0"						\
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 14f7826..c5b1565 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -366,13 +366,8 @@ static inline void tws_data_config_output(unsigned output)
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/ip04.h b/include/configs/ip04.h
new file mode 100644
index 0000000..425a745
--- /dev/null
+++ b/include/configs/ip04.h
@@ -0,0 +1,157 @@
+/*
+ * U-boot - Configuration file for IP04 board (having BF532 processor)
+ *
+ * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com
+ *
+ * Copyright (c) 2005-2010 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __CONFIG_IP04_H__
+#define __CONFIG_IP04_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf532-0.5
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_NAND
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			10000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			40
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			3
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	10
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	0x408
+#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL	0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL	0xffc2ffc2
+#define CONFIG_EBIU_AMBCTL1_VAL	0xffc2ffc2
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_NET_MULTI	1
+#define CONFIG_HOSTNAME		IP04
+
+#define CONFIG_DRIVER_DM9000	1
+#define CONFIG_DM9000_NO_SROM
+#define CONFIG_DM9000_BASE	0x20100000
+#define DM9000_IO		CONFIG_DM9000_BASE
+#define DM9000_DATA		(CONFIG_DM9000_BASE + 2)
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_SYS_NO_FLASH		/* we have only NAND */
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_WINBOND
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_PREBOOT		"echo starting from spi flash"
+#define CONFIG_ENV_OFFSET	0x30000
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+
+/*
+ * NAND Settings
+ */
+#define CONFIG_NAND_PLAT
+#define CONFIG_SYS_NAND_BASE		0x20000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
+#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
+#define BFIN_NAND_READY     PF10
+#define BFIN_NAND_WRITE(addr, cmd) \
+	do { \
+		bfin_write8(addr, cmd); \
+		SSYNC(); \
+	} while (0)
+
+#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
+#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
+#define NAND_PLAT_DEV_READY(chip)      (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY)
+#define NAND_PLAT_INIT() \
+	do { \
+		bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \
+		bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \
+		bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \
+		bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \
+	} while (0)
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_MISC_INIT_R	/* needed for MAC address */
+#define CONFIG_UART_CONSOLE	0
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+/* Enable this if bootretry required; currently it's disabled */
+#define CONFIG_BOOT_RETRY_TIME	-1
+#define CONFIG_BOOTCOMMAND	"run nandboot"
+#define CONFIG_AUTOBOOT_PROMPT	"autoboot in %d seconds\n"
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
index d0cb1e1..6903b36 100644
--- a/include/configs/ipek01.h
+++ b/include/configs/ipek01.h
@@ -324,13 +324,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index c013ac4..fb8ccae 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -37,6 +37,7 @@
 #define CONFIG_4xx			1	/* ... PPC4xx family	*/
 #define CONFIG_440			1	/* ... PPC440 family	*/
 #define CONFIG_440SPE			1	/* Specifc SPe support	*/
+#define CONFIG_440SPE_REVA		1	/* Support old Rev A.	*/
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
 #define CONFIG_SYS_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/
 
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index a79feec..e5537da 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -230,7 +230,7 @@
  *       SDRAM Controller DDR autocalibration values and takes a lot longer
  *       to run than Method_B.
  * (See the Method_A and Method_B algorithm discription in the file:
- *	cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
+ *	arch/ppc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
  * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
  *
  * DDR Autocalibration Method_B is the default.
diff --git a/include/configs/korat.h b/include/configs/korat.h
index 026dd08..f95df68 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -153,6 +153,7 @@
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h
index 16b464c..3958d09 100644
--- a/include/configs/linkstation.h
+++ b/include/configs/linkstation.h
@@ -290,7 +290,7 @@
  * taken from the orignal Linkstation boot code
  *
  * Most of the low level configuration setttings are normally used
- * in cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
+ * in arch/ppc/cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
  * Low level initialisation is done in board/linkstation/early_init.S
  * The values below are included for reference purpose only
  */
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 011dd5c..6461124 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -258,6 +258,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		100000		/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/magnesium.h b/include/configs/magnesium.h
new file mode 100644
index 0000000..4fb7744
--- /dev/null
+++ b/include/configs/magnesium.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
+ *
+ * based on:
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* include common defines/options for all imx27lite related boards */
+#include "imx27lite-common.h"
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MAGNESIUM
+#define CONFIG_HOSTNAME		magnesium
+#define CONFIG_BOARDNAME	"Projectiondesign magnesium\n"
+
+/*
+ * Flash & Environment
+ */
+#define CONFIG_SYS_FLASH_SECT_SZ	0x8000	/* 64KB sect size */
+#define CONFIG_ENV_OFFSET		(PHYS_FLASH_SIZE - 0x40000)
+#define PHYS_FLASH_SIZE			0x800000
+#define CONFIG_ENV_SECT_SIZE		0x20000		/* Env sector Size */
+
+/*
+ * NAND
+ */
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_MXC_MCI_REGS_BASE	0x10013000
+
+/*
+ * MTD partitions
+ */
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=mxc_nand.0"
+#define MTDPARTS_DEFAULT			\
+	"mtdparts="				\
+		"physmap-flash.0:"		\
+			"256k(U-Boot),"		\
+			"7680k(user),"		\
+			"128k(env1),"		\
+			"128k(env2);"		\
+		"mxc_nand.0:"			\
+			"128k(IPL-SPL),"	\
+			"4m(kernel),"		\
+			"22m(rootfs),"		\
+			"-(userfs)"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h
index b29ef9b..d25e093 100644
--- a/include/configs/manroland/mpc5200-common.h
+++ b/include/configs/manroland/mpc5200-common.h
@@ -170,13 +170,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
index 4a93b58..73405ea 100644
--- a/include/configs/mecp5200.h
+++ b/include/configs/mecp5200.h
@@ -63,9 +63,6 @@
 #endif
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-
-#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
-
 #define CONFIG_MII
 #if 0 /* test-only !!! */
 #define CONFIG_NET_MULTI	1
@@ -74,10 +71,6 @@
 #define CONFIG_NS8382X		1
 #endif
 
-#else	/* MPC5100 */
-
-#endif
-
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -152,12 +145,10 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
 
-#if defined(CONFIG_MPC5200)
 /*
  * IPB Bus clocking configuration.
  */
 #undef CONFIG_SYS_IPBSPEED_133			/* define for 133MHz speed */
-#endif
 /*
  * I2C configuration
  */
@@ -288,13 +279,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index d002b97..e085f4a 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -82,7 +82,6 @@
  */
 #include <config_cmd_default.h>
 #undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_LOADS
 #undef CONFIG_CMD_IMLS
diff --git a/include/configs/ml300.h b/include/configs/ml300.h
deleted file mode 100644
index 68d0c85..0000000
--- a/include/configs/ml300.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * ML300.h: ML300 specific config options
- *
- * http://www.xilinx.com/ml300
- *
- * Derived from : ML2.h
- *
- *     Author: Xilinx, Inc.
- *
- *
- *     This program is free software; you can redistribute it and/or modify it
- *     under the terms of the GNU General Public License as published by the
- *     Free Software Foundation; either version 2 of the License, or (at your
- *     option) any later version.
- *
- *
- *     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
- *     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
- *     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
- *     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
- *     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR
- *     OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
- *     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
- *     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
- *     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
- *     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
- *     FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- *     Xilinx products are not intended for use in life support appliances,
- *     devices, or systems. Use in such applications is expressly prohibited.
- *
- *
- *     (c) Copyright 2002 Xilinx Inc.
- *     All rights reserved.
- *
- *
- *     You should have received a copy of the GNU General Public License along
- *     with this program; if not, write to the Free Software Foundation, Inc.,
- *     675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* #define DEBUG */
-/* #define ET_DEBUG 1 */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_XILINX_405	1
-#define CONFIG_XILINX_ML300	1	/* ...on a Xilinx ML300 board	*/
-
-#define CONFIG_SYSTEMACE	1
-#define CONFIG_DOS_PARTITION	1
-#define CONFIG_SYS_SYSTEMACE_BASE	XPAR_OPB_SYSACE_0_BASEADDR
-#define CONFIG_SYS_SYSTEMACE_WIDTH	XPAR_XSYSACE_MEM_WIDTH
-
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* environment is in EEPROM */
-
-/* following are used only if env is in EEPROM */
-#ifdef	CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR	XPAR_PERSISTENT_0_IIC_0_EEPROMADDR
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_ENV_OFFSET		XPAR_PERSISTENT_0_IIC_0_BASEADDR
-#define CONFIG_MISC_INIT_R	1	/* used to call out convert_env() */
-#define CONFIG_ENV_OVERWRITE	1	/* allow users to update ethaddr and serial# */
-#endif
-
-#include "../board/xilinx/ml300/xparameters.h"
-
-#define CONFIG_SYS_NO_FLASH		1	/* no flash */
-#define CONFIG_ENV_SIZE		XPAR_PERSISTENT_0_IIC_0_HIGHADDR - XPAR_PERSISTENT_0_IIC_0_BASEADDR + 1
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command	*/
-
-#define CONFIG_BOOTARGS		"console=ttyS0,9600 ip=off " \
-				"root=/dev/xsysace/disc0/part3 rw"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_NET
-
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_IMLS
-
-
-/* #define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ */
-/* 300000000 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt	*/
-
-#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size	*/
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_SYS_DUART_CHAN		0
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550 1
-#define CONFIG_SYS_INIT_CHAN1	 1
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_MONITOR_BASE	0x04000000
-#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR	0x800000  /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END	0x2000	  /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128	  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02	/* Software reboot			*/
-
-#endif				/* __CONFIG_H */
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 903fe6d..3626df7 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -160,6 +160,9 @@
 #define PHYS_SDRAM_1		CSD0_BASE_ADDR
 #define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
 
+#define CONFIG_SYS_DDR_CLKSEL	0
+#define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
+
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h
index 4bed7ae..cb7efe7 100644
--- a/include/configs/netstal-common.h
+++ b/include/configs/netstal-common.h
@@ -42,6 +42,7 @@
  * I2C
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 18e7cc2..bdc0f79 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -138,7 +138,6 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#if defined(CONFIG_MPC5200)
 /*
  * IPB Bus clocking configuration.
  */
@@ -154,7 +153,6 @@
  */
 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
-#endif
 
 /*
  * I2C configuration
@@ -276,13 +274,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/otc570.h b/include/configs/otc570.h
index 8e27eba..fb0f576 100644
--- a/include/configs/otc570.h
+++ b/include/configs/otc570.h
@@ -102,6 +102,7 @@
 	at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \
 	at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \
 }
+#define I2C_SOFT_DECLARATIONS
 /* Configure data pin as output */
 #define I2C_ACTIVE		at91_set_pio_output(AT91_PIO_PORTB, 4, 0)
 /* Configure data pin as input */
@@ -130,7 +131,6 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
-#undef CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_LOADS
 #undef CONFIG_CMD_IMLS
diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
index 729ca6a..d6b9207 100644
--- a/include/configs/p3p440.h
+++ b/include/configs/p3p440.h
@@ -92,6 +92,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs	*/
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index 000ae5c..1f744b8 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -138,6 +138,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
index 8ca55d7..80a0bc6 100644
--- a/include/configs/pf5200.h
+++ b/include/configs/pf5200.h
@@ -61,7 +61,6 @@
 #endif
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
-#ifdef CONFIG_MPC5200		/* MPC5100 PCI is not supported yet. */
 /*
  * PCI Mapping:
  * 0x40000000 - 0x4fffffff - PCI Memory
@@ -87,7 +86,6 @@
 #define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
 #define CONFIG_NS8382X		1
 #endif
-#endif
 
 /* Partitions */
 #define CONFIG_MAC_PARTITION
@@ -121,9 +119,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IDE
 
-#ifdef CONFIG_MPC5200
 #define CONFIG_CMD_PCI
-#endif
 
 
 #if (TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
@@ -166,12 +162,10 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
 
-#if defined(CONFIG_MPC5200)
 /*
  * IPB Bus clocking configuration.
  */
 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
-#endif
 /*
  * I2C configuration
  */
@@ -289,13 +283,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 47bb8c0..a0b00e9 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -28,8 +28,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_AT91_LEGACY
-
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9261"
 
@@ -51,26 +49,26 @@
 /* clocks */
 /* CKGR_MOR - enable main osc. */
 #define CONFIG_SYS_MOR_VAL						\
-		(AT91_PMC_MOSCEN |					\
+		(AT91_PMC_MOR_MOSCEN |					\
 		 (255 << 8))		/* Main Oscillator Start-up Time */
 #define CONFIG_SYS_PLLAR_VAL						\
-		(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
-		 AT91_PMC_OUT |						\
+		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
+		 AT91_PMC_PLLXR_OUT(3) |						\
 		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
 
 /* PCK/2 = MCK Master Clock from PLLA */
 #define	CONFIG_SYS_MCKR1_VAL		\
-		(AT91_PMC_CSS_SLOW |	\
-		 AT91_PMC_PRES_1 |	\
-		 AT91SAM9_PMC_MDIV_2 |	\
-		 AT91_PMC_PDIV_1)
+		(AT91_PMC_MCKR_CSS_SLOW |	\
+		 AT91_PMC_MCKR_PRES_1 |	\
+		 AT91_PMC_MCKR_MDIV_2 |	\
+		 AT91_PMC_MCKR_PLLADIV_1)
 
 /* PCK/2 = MCK Master Clock from PLLA */
 #define	CONFIG_SYS_MCKR2_VAL		\
-		(AT91_PMC_CSS_PLLA |	\
-		 AT91_PMC_PRES_1 |	\
-		 AT91SAM9_PMC_MDIV_2 |	\
-		 AT91_PMC_PDIV_1)
+		(AT91_PMC_MCKR_CSS_PLLA |	\
+		 AT91_PMC_MCKR_PRES_1 |	\
+		 AT91_PMC_MCKR_MDIV_2 |	\
+		 AT91_PMC_MCKR_PLLADIV_1)
 
 /* define PDC[31:16] as DATA[31:16] */
 #define CONFIG_SYS_PIOC_PDR_VAL1	0xFFFF0000
@@ -79,7 +77,7 @@
 
 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
 #define CONFIG_SYS_MATRIX_EBICSA_VAL		\
-       (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC)
+	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
 
 /* SDRAM */
 /* SDRAMC_MR Mode register */
@@ -122,32 +120,32 @@
 
 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
 #define CONFIG_SYS_SMC0_SETUP0_VAL					\
-		(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |	\
-		 AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
+		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
+		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
 #define CONFIG_SYS_SMC0_PULSE0_VAL					\
-		(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |	\
-		 AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
+		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
 #define CONFIG_SYS_SMC0_CYCLE0_VAL	\
-		(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
 #define CONFIG_SYS_SMC0_MODE0_VAL				\
-		(AT91_SMC_READMODE | AT91_SMC_WRITEMODE |	\
-		 AT91_SMC_DBW_16 |				\
-		 AT91_SMC_TDFMODE |				\
-		 AT91_SMC_TDF_(6))
+		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
+		 AT91_SMC_MODE_DBW_16 |				\
+		 AT91_SMC_MODE_TDF |				\
+		 AT91_SMC_MODE_TDF_CYCLE(6))
 
 /* user reset enable */
 #define CONFIG_SYS_RSTC_RMR_VAL			\
 		(AT91_RSTC_KEY |		\
-		AT91_RSTC_PROCRST |		\
-		AT91_RSTC_RSTTYP_WAKEUP |	\
-		AT91_RSTC_RSTTYP_WATCHDOG)
+		AT91_RSTC_CR_PROCRST |		\
+		AT91_RSTC_MR_ERSTL(1) |	\
+		AT91_RSTC_MR_ERSTL(2))
 
 /* Disable Watchdog */
 #define CONFIG_SYS_WDTC_WDMR_VAL				\
-		(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |	\
-		 AT91_WDT_WDV |					\
-		 AT91_WDT_WDDIS |				\
-		 AT91_WDT_WDD)
+		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
+		 AT91_WDT_MR_WDV(0xfff) |					\
+		 AT91_WDT_MR_WDDIS |				\
+		 AT91_WDT_MR_WDD(0xfff))
 
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS 1
@@ -180,9 +178,9 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define	CONFIG_RED_LED		AT91_PIN_PC12
-#define	CONFIG_GREEN_LED	AT91_PIN_PC13
-#define	CONFIG_YELLOW_LED	AT91_PIN_PC15
+#define	CONFIG_RED_LED		AT91_PIO_PORTC, 12
+#define	CONFIG_GREEN_LED	AT91_PIO_PORTC, 13
+#define	CONFIG_YELLOW_LED	AT91_PIO_PORTC, 15
 
 #define CONFIG_BOOTDELAY	3
 
@@ -200,7 +198,6 @@
 #include <config_cmd_default.h>
 #undef CONFIG_CMD_BDI
 #undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_LOADS
 #undef CONFIG_CMD_IMLS
@@ -236,8 +233,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
 /* our CLE is AD21 */
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA16
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTC, 14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 16
 
 /* NOR flash */
 #define CONFIG_SYS_FLASH_CFI			1
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 807dba8..f854f38 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -215,7 +215,6 @@
 #include <config_cmd_default.h>
 #undef CONFIG_CMD_BDI
 #undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_LOADS
 #undef CONFIG_CMD_IMLS
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
index b08dcd4..2472187 100644
--- a/include/configs/quad100hd.h
+++ b/include/configs/quad100hd.h
@@ -150,6 +150,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
@@ -232,7 +233,7 @@
  * Definitions for initial stack pointer and data area (in data cache)
  */
 /* use on chip memory (OCM) for temperary stack until sdram is tested */
-/* see ./cpu/ppc4xx/start.S */
+/* see ./arch/ppc/cpu/ppc4xx/start.S */
 #define CONFIG_SYS_TEMP_STACK_OCM	1
 
 /* On Chip Memory location */
@@ -250,7 +251,7 @@
  * Taken from PPCBoot board/icecube/icecube.h
  */
 
-/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
+/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
 #define CONFIG_SYS_EBC_PB0AP		0x04002480
 /* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
 #define CONFIG_SYS_EBC_PB0CR		0xFFC5A000
@@ -268,7 +269,7 @@
  *
  * Taken in part from PPCBoot board/icecube/icecube.h
  */
-/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
+/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
 #define CONFIG_SYS_GPIO0_OSRH		0x55555550
 #define CONFIG_SYS_GPIO0_OSRL		0x00000110
 #define CONFIG_SYS_GPIO0_ISR1H		0x00000000
diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h
index 242f42f..429b11c 100644
--- a/include/configs/sbc405.h
+++ b/include/configs/sbc405.h
@@ -166,6 +166,7 @@
 
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
 #undef  CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index a5eca39..7423663 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -251,6 +251,7 @@
  */
 #define  CONFIG_HARD_I2C		/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 
 #define I2C_INIT
 #define I2C_ACTIVE 0
@@ -455,7 +456,7 @@
  * - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR
  * - Stackpointer will be located to
  *   (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF)
- *   in cpu/ppc4xx/start.S
+ *   in arch/ppc/cpu/ppc4xx/start.S
  */
 
 #undef CONFIG_SYS_INIT_DCACHE_CS
@@ -494,7 +495,7 @@
 #define BOOTFLAG_WARM	0x02		/* Software reboot			*/
 
 /* ################################################################################### */
-/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects  */
+/* These defines will be used in arch/ppc/cpu/ppc4xx/cpu_init.c to setup external chip selects  */
 /* They are currently undefined cause they are initiaized in board/solidcard3/init.S   */
 
 /* This chip select accesses the boot device */
diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h
index 5a2ef3a..060026b 100644
--- a/include/configs/smmaco4.h
+++ b/include/configs/smmaco4.h
@@ -358,13 +358,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index 27dda25..d377e19 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -438,13 +438,8 @@
 /*
  * Various low-level settings
  */
-#if defined(CONFIG_MPC5200)
 #define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CONFIG_SYS_HID0_FINAL		HID0_ICE
-#else
-#define CONFIG_SYS_HID0_INIT		0
-#define CONFIG_SYS_HID0_FINAL		0
-#endif
 
 #define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index 5a5fbdd..409a042 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -105,11 +105,11 @@
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-	cpu/blackfin/traps.o		(.text .text.*); \
-	cpu/blackfin/interrupt.o	(.text .text.*); \
-	cpu/blackfin/serial.o		(.text .text.*); \
+	arch/blackfin/cpu/traps.o		(.text .text.*); \
+	arch/blackfin/cpu/interrupt.o	(.text .text.*); \
+	arch/blackfin/cpu/serial.o		(.text .text.*); \
 	common/dlmalloc.o		(.text .text.*); \
-	lib_generic/crc32.o		(.text .text.*); \
+	lib/crc32.o		(.text .text.*); \
 	. = DEFINED(env_offset) ? env_offset : .; \
 	common/env_embedded.o		(.text .text.*);
 #endif
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index 92bcdb3..d462ed0 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -170,12 +170,10 @@
 
 #define CONFIG_BOOTCOMMAND	"run net_nfs"
 
-#if defined(CONFIG_MPC5200)
 /*
  * IPB Bus clocking configuration.
  */
 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK			/* define for 133MHz speed */
-#endif
 
 /*
  * I2C configuration
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 42f8807..0b4dfb8 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -37,6 +37,7 @@
 #define CONFIG_4xx			1	/* ... PPC4xx family	*/
 #define CONFIG_440			1	/* ... PPC440 family	*/
 #define CONFIG_440SPE			1	/* Specifc SPe support	*/
+#define CONFIG_440SPE_REVA		1	/* Support old Rev A.	*/
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init	*/
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
 #define EXTCLK_33_33		33333333
diff --git a/include/configs/zeus.h b/include/configs/zeus.h
index 1a77c71..3b2aede 100644
--- a/include/configs/zeus.h
+++ b/include/configs/zeus.h
@@ -167,6 +167,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
 #define CONFIG_SYS_I2C_SLAVE		0x7F
author	Minkyu Kang <mk7.kang@samsung.com>	2010-04-19 10:26:18 +0900
committer	Minkyu Kang <mk7.kang@samsung.com>	2010-04-19 10:26:18 +0900
commit	83653121d7382fccfe329cb732f77f116341ef1d (patch)
tree	0b1ce6764252af15dfb2614372de98a44a7ec61f /include/configs
parent	0f1f21a345e02a68ec16f7ab9e7dc687f9276089 (diff)
parent	07739bcef5da07cc4a4edef8b91014ccc332eda3 (diff)
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