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authorWolfgang Denk <wd@denx.de>2011-10-21 23:48:46 +0200
committerWolfgang Denk <wd@denx.de>2011-10-21 23:48:46 +0200
commit02aff558f4b68927c719a33bee8d13d325d105fb (patch)
tree215757279d23a8984cad993679c6be20fe0d6831 /include/configs
parentf82c087e60fe1c59ace1c6f016eb89c5d3c3ae13 (diff)
parent710308ee185b3087e474fb9b205f47613c65dda4 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx: mpc85xx: Add inline GPIO acessor functions powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9) powerpc/85xx: Fix P2020DS booting powerpc/85xx: Update USB device tree status based on pin settings fdt: Add new fdt_set_node_status & fdt_set_status_by_alias helpers powerpc/85xx: Add support for RMan LIODN initialization powerpc/85xx: Update device tree handling for SRIO powerpc/85xx: Update setting of SRIO LIODNs fm: Don't allow disabling of FM1-DTSEC1 fm-eth: Don't mark the MAC we use for MDIO as disabled in device tree
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/P2041RDB.h1
-rw-r--r--include/configs/P3041DS.h1
-rw-r--r--include/configs/P5020DS.h1
3 files changed, 3 insertions, 0 deletions
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 91c250f..337e8df 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -66,6 +66,7 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
+#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CONFIG_FSL_LAW /* Use common FSL init code */
diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
index e4d1fe5..57d5de5 100644
--- a/include/configs/P3041DS.h
+++ b/include/configs/P3041DS.h
@@ -35,6 +35,7 @@
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
+#define CONFIG_SYS_DPAA_RMAN
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
index 618d1a4..a9cee23 100644
--- a/include/configs/P5020DS.h
+++ b/include/configs/P5020DS.h
@@ -36,6 +36,7 @@
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_FSL_RAID_ENGINE
+#define CONFIG_SYS_DPAA_RMAN
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */