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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-08-05 07:59:35 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-08-28 17:12:36 -0500 |
| commit | ad19e7a5d2de337064ce7728d6504df9648f5d31 (patch) | |
| tree | b9f8344338ac6397703851476bec6b43b55847f0 /include/configs | |
| parent | 8295b94400449586505ffe34ec024feb3d2c8fe4 (diff) | |
| download | u-boot-imx-ad19e7a5d2de337064ce7728d6504df9648f5d31.zip u-boot-imx-ad19e7a5d2de337064ce7728d6504df9648f5d31.tar.gz u-boot-imx-ad19e7a5d2de337064ce7728d6504df9648f5d31.tar.bz2 | |
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory
The old PCI ATMU setup code would just mimic the PCI regions into the
ATMU registers. For simple memory maps in which all memory, MMIO, etc
space fit into 4G this works ok. However there are issues with we have
>4G of memory as we know can't access all of memory and we need to
ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with
anything since we can't turn it off.
We first setup outbound windows based on what the board code setup
in the pci regions for MMIO and IO access. Next we place PCICSRBAR
below the MMIO window. After which we try to setup the inbound windows
to map as much of memory as possible.
On PCIe based controllers we are able to overmap the ATMU setup since
RX & TX links are separate but report the proper amount of inbound
address space to the region tracking to ensure there is no overlap.
On PCI based controllers we use as many inbound windows as available to
map as much of the memory as possible.
Additionally we changed all the CCSR register access to use proper IO
accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some
86xx platforms that didn't have it defined.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/MPC8610HPCD.h | 1 | ||||
| -rw-r--r-- | include/configs/sbc8641d.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index a3b5c7c..44ff289 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -81,6 +81,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index ef0f627..abc449d 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -107,6 +107,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) |