Merge branch 'master' of git://www.denx.de/git/u-boot-sh

4 files changed, 558 insertions, 0 deletions

diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
new file mode 100644
index 0000000..99e1179
--- /dev/null
+++ b/include/configs/MigoR.h
@@ -0,0 +1,151 @@
+/*
+ * Configuation settings for the Renesas Solutions Migo-R board
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MIGO_R_H
+#define __MIGO_R_H
+
+#undef DEBUG
+#define CONFIG_SH		1
+#define CONFIG_SH4		1
+#define CONFIG_CPU_SH7722	1
+#define CONFIG_MIGO_R		1
+
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_ENV
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC0,115200 root=1f01"
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.10.100
+#define CONFIG_SERVERIP		192.168.10.77
+#define CONFIG_GATEWAYIP	192.168.10.77
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* SMC9111 */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE    (0xB0000000)
+
+/* MEMORY */
+#define MIGO_R_SDRAM_BASE	(0x8C000000)
+#define MIGO_R_FLASH_BASE_1	(0xA0000000)
+#define MIGO_R_FLASH_BANK_SIZE	(64 * 1024 * 1024)
+
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256		/* Buffer size for input from the Console */
+#define CFG_PBSIZE		256		/* Buffer size for Console output */
+#define CFG_MAXARGS		16		/* max args accepted for monitor commands */
+#define CFG_BARGSIZE	512		/* Buffer size for Boot Arguments passed to kernel */
+#define CFG_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
+
+/* SCIF */
+#define CFG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF0	1
+#undef  CFG_CONSOLE_INFO_QUIET	/* Suppress display of console
+								   information at boot */
+#undef  CFG_CONSOLE_OVERWRITE_ROUTINE
+#undef  CFG_CONSOLE_ENV_OVERWRITE
+
+#define CFG_MEMTEST_START	(MIGO_R_SDRAM_BASE)
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Enable alternate, more extensive, memory test */
+#undef  CFG_ALT_MEMTEST
+/* Scratch address used by the alternate memory test */
+#undef  CFG_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef  CFG_LOADS_BAUD_CHANGE
+
+#define CFG_SDRAM_BASE	(MIGO_R_SDRAM_BASE)
+/* maybe more, but if so u-boot doesn't know about it... */
+#define CFG_SDRAM_SIZE	(64 * 1024 * 1024)
+/* default load address for scripts ?!? */
+#define CFG_LOAD_ADDR	(CFG_SDRAM_BASE + 16 * 1024 * 1024)
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CFG_MONITOR_BASE	(MIGO_R_FLASH_BASE_1)
+/* Monitor size */
+#define CFG_MONITOR_LEN	(128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN	(256 * 1024)
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE	(256)
+#define CFG_BOOTMAPSZ	(8 * 1024 * 1024)
+
+/* FLASH */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef  CFG_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO
+/* Physical start address of Flash memory */
+#define CFG_FLASH_BASE	(MIGO_R_FLASH_BASE_1)
+/* Max number of sectors on each Flash chip */
+#define CFG_MAX_FLASH_SECT	512
+
+/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
+#define CFG_MAX_FLASH_BANKS	1
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
+
+/* Timeout for Flash erase operations (in ms) */
+#define CFG_FLASH_ERASE_TOUT	(3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CFG_FLASH_WRITE_TOUT	(3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CFG_FLASH_LOCK_TOUT	(3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT	(3 * 1000)
+
+/* Use hardware flash sectors protection instead of U-Boot software protection */
+#undef  CFG_FLASH_PROTECTION
+#undef  CFG_DIRECT_FLASH_TFTP
+
+/* ENV setting */
+#define CFG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CFG_ENV_SECT_SIZE	(128 * 1024)
+#define CFG_ENV_SIZE		(CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+/* Offset of env Flash sector relative to CFG_FLASH_BASE */
+#define CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */
+#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+#endif	/* __MIGO_R_H */
diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h
new file mode 100644
index 0000000..0fc0b97
--- /dev/null
+++ b/include/configs/mpr2.h
@@ -0,0 +1,92 @@
+/*
+ * Configuation settings for MPR2
+ *
+ * Copyright (C) 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MPR2_H
+#define __MPR2_H
+
+/* Supported commands */
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_FLASH
+
+/* Default environment variables */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTARGS		"console=ttySC0,115200"
+#define CONFIG_BOOTFILE		/boot/zImage
+#define CONFIG_LOADADDR		0x8E000000
+#define CONFIG_VERSION_VARIABLE
+
+/* CPU and platform */
+#define CONFIG_SH		1
+#define CONFIG_SH3		1
+#define CONFIG_CPU_SH7720	1
+#define CONFIG_MPR2		1
+
+/* U-Boot internals */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256	/* Buffer size for input from the Console */
+#define CFG_PBSIZE		256	/* Buffer size for Console output */
+#define CFG_MAXARGS		16	/* max args accepted for monitor commands */
+#define CFG_BARGSIZE		512	/* Buffer size for Boot Arguments passed to kernel */
+#define CFG_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
+#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 32 * 1024 * 1024)
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(128 * 1024)
+#define CFG_MALLOC_LEN		(256 * 1024)
+#define CFG_GBL_DATA_SIZE	256
+
+/* Memory */
+#define CFG_SDRAM_BASE		0x8C000000
+#define CFG_SDRAM_SIZE		(64 * 1024 * 1024)
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Flash */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_BASE		0xA0000000
+#define CFG_MAX_FLASH_SECT	256
+#define CFG_MAX_FLASH_BANKS	1
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	(128 * 1024)
+#define CFG_ENV_SIZE		CFG_ENV_SECT_SIZE
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT	120000
+#define CFG_FLASH_WRITE_TOUT	500
+
+/* Clocks */
+#define CONFIG_SYS_CLK_FREQ	24000000
+#define TMU_CLK_DIVIDER		4	/* 4 (default), 16, 64, 256 or 1024 */
+#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+/* UART */
+#define CFG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF0	1
+
+#endif	/* __MPR2_H */
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
new file mode 100644
index 0000000..c20baca
--- /dev/null
+++ b/include/configs/r2dplus.h
@@ -0,0 +1,150 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+#define CONFIG_SH		1
+#define CONFIG_SH4		1
+#define CONFIG_CPU_SH7751	1
+#define CONFIG_CPU_SH_TYPE_R	1
+#define CONFIG_R2DPLUS		1
+#define __LITTLE_ENDIAN__	1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+
+/* SCIF */
+#define CFG_SCIF_CONSOLE	1
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_CONS_SCIF1	1
+#define BOARD_LATE_INIT		1
+
+#define CONFIG_BOOTDELAY	-1
+#define CONFIG_BOOTARGS		"console=ttySC0,115200"
+#define CONFIG_ENV_OVERWRITE	1
+
+/* Network setting */
+#define CONFIG_NETMASK		255.0.0.0
+#define CONFIG_IPADDR		10.0.192.51
+#define CONFIG_SERVERIP		10.0.0.1
+#define CONFIG_GATEWAYIP	10.0.0.1
+
+/* SDRAM */
+#define CFG_SDRAM_BASE		(0x8C000000)
+#define CFG_SDRAM_SIZE		(0x04000000)
+
+#define CFG_LONGHELP
+#define CFG_PROMPT		"=> "
+#define CFG_CBSIZE		256
+#define CFG_PBSIZE		256
+#define CFG_MAXARGS		16
+#define CFG_BARGSIZE		512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_MEMTEST_START	(CFG_SDRAM_BASE)
+#define CFG_MEMTEST_END		(TEXT_BASE - 0x100000)
+
+#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 32 * 1024 * 1024)
+/* Address of u-boot image in Flash */
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE)
+#define CFG_MONITOR_LEN		(128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN		(256 * 1024)
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE	(256)
+#define CFG_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/*
+ * NOR Flash
+ */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+
+#if defined(CONFIG_R2DPLUS_OLD)
+#define CFG_FLASH_BASE		(0xA0000000)
+#define CFG_MAX_FLASH_BANKS (1)	/* Max number of
+				 * Flash memory banks
+				 */
+#define CFG_MAX_FLASH_SECT  142
+#define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
+
+#else /* CONFIG_R2DPLUS_OLD */
+
+#define CFG_FLASH_BASE		(0xA0000000)
+#define CFG_FLASH_CFI_WIDTH	0x04	/* 32bit */
+#define CFG_MAX_FLASH_BANKS	(2)
+#define CFG_MAX_FLASH_SECT	270
+#define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE,\
+			CFG_FLASH_BASE + 0x100000,\
+			CFG_FLASH_BASE + 0x400000,\
+			CFG_FLASH_BASE + 0x700000, }
+#endif /* CONFIG_R2DPLUS_OLD */
+
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_SIZE		(CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT	120000
+#define CFG_FLASH_WRITE_TOUT	500
+
+/*
+ * SuperH Clock setting
+ */
+#define CONFIG_SYS_CLK_FREQ	60000000
+#define TMU_CLK_DIVIDER		4
+#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define	CFG_PLL_SETTLING_TIME	100/* in us */
+
+/*
+ * IDE support
+ */
+#define CONFIG_IDE_RESET	1
+#define CFG_PIO_MODE		1
+#define CFG_IDE_MAXBUS		1 /* IDE bus */
+#define CFG_IDE_MAXDEVICE	1
+#define CFG_ATA_BASE_ADDR	0xb4000000
+#define CFG_ATA_STRIDE		2 /* 1bit shift */
+#define CFG_ATA_DATA_OFFSET	0x1000	/* data reg offset */
+#define CFG_ATA_REG_OFFSET	0x1000	/* reg offset */
+#define CFG_ATA_ALT_OFFSET	0x800	/* alternate register offset */
+
+/*
+ * SuperH PCI Bridge Configration
+ */
+#define CONFIG_PCI
+#define CONFIG_SH4_PCI
+#define CONFIG_SH7751_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW	1
+#define __io
+#define __mem_pci
+
+#define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */
+#define CONFIG_PCI_IO_BUS	0xFE240000	/* IO space base address */
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x00040000	/* Size of IO window */
+
+/*
+ * Network device (RTL8139) support
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_RTL8139
+#define _IO_BASE		0x00000000
+#define KSEG1ADDR(x)		(x)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
new file mode 100644
index 0000000..42787f4
--- /dev/null
+++ b/include/configs/r7780mp.h
@@ -0,0 +1,165 @@
+/*
+ * Configuation settings for the Renesas R7780MP board
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __R7780RP_H
+#define __R7780RP_H
+
+#undef DEBUG
+#define CONFIG_SH		1
+#define CONFIG_SH4A		1
+#define CONFIG_CPU_SH7780	1
+#define CONFIG_R7780MP		1
+#define __LITTLE_ENDIAN 1
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+
+#define CFG_SCIF_CONSOLE	1
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_CONS_SCIF0	1
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC0,115200"
+#define CONFIG_ENV_OVERWRITE	1
+
+/* check for keypress on bootdelay==0 */
+/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
+
+/* Network setting */
+#define CONFIG_NETMASK		255.0.0.0
+#define CONFIG_IPADDR		10.0.192.82
+#define CONFIG_SERVERIP		10.0.0.1
+#define CONFIG_GATEWAYIP	10.0.0.1
+
+#define CFG_SDRAM_BASE		(0x08000000)
+#define CFG_SDRAM_SIZE		(128 * 1024 * 1024)
+
+#define CFG_LONGHELP
+#define CFG_PROMPT		"=> "
+#define CFG_CBSIZE		256
+#define CFG_PBSIZE		256
+#define CFG_MAXARGS		16
+#define CFG_BARGSIZE	512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_MEMTEST_START	(CFG_SDRAM_BASE)
+#define CFG_MEMTEST_END		(TEXT_BASE - 0x100000)
+
+/* NOR Flash (S29PL127J60TFI130) */
+#define CFG_FLASH_BASE		(0xA0000000)
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+#define CFG_MAX_FLASH_BANKS (2)
+#define CFG_MAX_FLASH_SECT  270
+#define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE,\
+				CFG_FLASH_BASE + 0x100000,\
+				CFG_FLASH_BASE + 0x400000,\
+				CFG_FLASH_BASE + 0x700000, }
+
+#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 4 * 1024 * 1024)
+/* Address of u-boot image in Flash */
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE)
+#define CFG_MONITOR_LEN		(112 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN		(256 * 1024)
+
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE	(256)
+#define CFG_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CFG_RX_ETH_BUFFER	(8)
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef CFG_FLASH_CFI_BROKEN_TABLE
+#undef  CFG_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO
+
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	(16 * 1024)
+#define CFG_ENV_SIZE		(CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT  	120000
+#define CFG_FLASH_WRITE_TOUT	500
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define TMU_CLK_DIVIDER		4
+#define CFG_HZ	(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+/* PCI Controller */
+#if defined(CONFIG_CMD_PCI)
+#define CONFIG_PCI
+#define CONFIG_SH4_PCI
+#define CONFIG_SH7780_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW	1
+#define __io
+#define __mem_pci
+
+#define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */
+
+#define CONFIG_PCI_IO_BUS	0xFE200000	/* IO space base address */
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x00200000	/* Size of IO window */
+#endif /* CONFIG_CMD_PCI */
+
+#if defined(CONFIG_CMD_NET)
+/* #define CONFIG_NET_MULTI
+   #define CONFIG_RTL8169 */
+/* AX88696L Support(NE2000 base chip) */
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_AX88796L
+#define CONFIG_DRIVER_NE2000_BASE	0xA4100000
+#endif
+
+/* Compact flash Support */
+#if defined(CONFIG_CMD_IDE)
+#define CONFIG_IDE_RESET        1
+#define CFG_PIO_MODE            1
+#define CFG_IDE_MAXBUS          1   /* IDE bus */
+#define CFG_IDE_MAXDEVICE       1
+#define CFG_ATA_BASE_ADDR       0xb4000000
+#define CFG_ATA_STRIDE          2               /* 1bit shift */
+#define CFG_ATA_DATA_OFFSET     0x1000          /* data reg offset */
+#define CFG_ATA_REG_OFFSET      0x1000          /* reg offset */
+#define CFG_ATA_ALT_OFFSET      0x800           /* alternate register offset */
+#endif /* CONFIG_CMD_IDE */
+
+#endif /* __R7780RP_H */