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authorWolfgang Denk <wd@denx.de>2010-10-25 08:06:52 +0200
committerWolfgang Denk <wd@denx.de>2010-10-25 08:06:52 +0200
commitc163f4478ca72f51b28b55f74addc8fe029d7b83 (patch)
tree914495b79944d55ff161fd7611d46ee7ab523978 /include/configs
parent9038e0e7029e47ec1700128351281225f711545e (diff)
parent6d79c39958aa0245e59f33860cd1ddd589119968 (diff)
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Merge branch 'master' of ssh://gemini/home/wd/git/u-boot/master
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/KUP4K.h6
-rw-r--r--include/configs/KUP4X.h6
-rw-r--r--include/configs/MVBLM7.h2
-rw-r--r--include/configs/TB5200.h8
-rw-r--r--include/configs/TQM5200.h8
-rw-r--r--include/configs/a4m072.h59
-rw-r--r--include/configs/cerf250.h14
-rw-r--r--include/configs/cm5200.h4
-rw-r--r--include/configs/colibri_pxa270.h2
-rw-r--r--include/configs/corenet_ds.h2
-rw-r--r--include/configs/cradle.h18
-rw-r--r--include/configs/csb226.h7
-rw-r--r--include/configs/delta.h267
-rw-r--r--include/configs/innokom.h8
-rw-r--r--include/configs/lubbock.h8
-rw-r--r--include/configs/lwmon.h50
-rw-r--r--include/configs/lwmon5.h15
-rw-r--r--include/configs/palmld.h1
-rw-r--r--include/configs/palmtc.h1
-rw-r--r--include/configs/pleb2.h18
-rw-r--r--include/configs/pxa255_idp.h8
-rw-r--r--include/configs/sh7785lcr.h6
-rw-r--r--include/configs/spieval.h8
-rw-r--r--include/configs/trizepsiv.h1
-rw-r--r--include/configs/vision2.h14
-rw-r--r--include/configs/vpac270.h1
-rw-r--r--include/configs/wepep250.h199
-rw-r--r--include/configs/xaeniax.h9
-rw-r--r--include/configs/xm250.h9
-rw-r--r--include/configs/xpedite1000.h (renamed from include/configs/XPEDITE1000.h)5
-rw-r--r--include/configs/xpedite517x.h (renamed from include/configs/XPEDITE5170.h)37
-rw-r--r--include/configs/xpedite520x.h (renamed from include/configs/XPEDITE5200.h)26
-rw-r--r--include/configs/xpedite537x.h (renamed from include/configs/XPEDITE5370.h)35
-rw-r--r--include/configs/xpedite550x.h607
-rw-r--r--include/configs/xsengine.h216
-rw-r--r--include/configs/zipitz2.h1
36 files changed, 863 insertions, 823 deletions
diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h
index 9702d63..c8e0ff2 100644
--- a/include/configs/KUP4K.h
+++ b/include/configs/KUP4K.h
@@ -139,9 +139,9 @@
/* List of I2C addresses to be verified by POST */
-#define I2C_ADDR_LIST {CONFIG_SYS_I2C_PICIO_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- }
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR, \
+ }
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h
index 9613ed9..ce731e3 100644
--- a/include/configs/KUP4X.h
+++ b/include/configs/KUP4X.h
@@ -149,9 +149,9 @@
/* List of I2C addresses to be verified by POST */
-#define I2C_ADDR_LIST {CONFIG_SYS_I2C_PICIO_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- }
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR, \
+ }
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 04d97cd..44d45e3 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -324,7 +324,7 @@
#define CONFIG_SYS_SCCR_TSEC1CM 1
#define CONFIG_SYS_SCCR_TSEC2CM 1
-#define CONFIG_SYS_SICRH 0x1fff8003
+#define CONFIG_SYS_SICRH 0x1fef0003
#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
#define CONFIG_SYS_HID0_INIT 0x000000000
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index ad86e2e..f336e8d 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -251,10 +251,10 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/* List of I2C addresses to be verified by POST */
-#undef I2C_ADDR_LIST
-#define I2C_ADDR_LIST { CONFIG_SYS_I2C_EEPROM_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_SLAVE }
+#undef CONFIG_SYS_POST_I2C_ADDRS
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR, \
+ CONFIG_SYS_I2C_SLAVE}
/*
* Flash configuration
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 2612c7a..794e11b 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -370,10 +370,10 @@
/* List of I2C addresses to be verified by POST */
#if defined (CONFIG_MINIFAP)
-#undef I2C_ADDR_LIST
-#define I2C_ADDR_LIST { CONFIG_SYS_I2C_EEPROM_ADDR, \
- CONFIG_SYS_I2C_HWMON_ADDR, \
- CONFIG_SYS_I2C_SLAVE }
+#undef CONFIG_SYS_POST_I2C_ADDRS
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_HWMON_ADDR, \
+ CONFIG_SYS_I2C_SLAVE}
#endif
/*
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
index 24a04eb..f18bc45 100644
--- a/include/configs/a4m072.h
+++ b/include/configs/a4m072.h
@@ -147,27 +147,43 @@
#define CONFIG_PREBOOT "run try_update"
#define CONFIG_EXTRA_ENV_SETTINGS \
- "bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \
- "cf1=diskboot 200000 0:1\0" \
- "bootcmd_cf1=run bcf1\0" \
- "bcf=setenv bootargs root=/dev/hda3\0" \
- "bootcmd_nfs=run bnfs\0" \
- "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs\0" \
- "bootcmd_nor=cp.b ${kernel_addr} 200000 100000; run norargs addip; run bk\0" \
- "bnfs=nfs 200000 ${rootpath}/boot/uImage ; run nfsargs addip ; run bk\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
- "try_update=usb start;sleep 2;usb start;sleep 1;fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;source 2F0000\0" \
- "env_addr=FE060000\0" \
- "kernel_addr=FE100000\0" \
- "rootfs_addr=FE200000\0" \
- "add_mtd=setenv bootargs ${bootargs} mtdparts=phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \
- "bcf1=run cf1; run bcf; run addip; run bk\0" \
- "add_consolespec=setenv bootargs ${bootargs} console=/dev/null quiet\0" \
- "addip=if test \"${ethaddr}\" != \"00:00:00:00:00:00\" ; then if test -n ${ipaddr}; then setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off panic=1; fi ; fi\0" \
- "hostname=CPUP0\0" \
- "ethaddr=00:00:00:00:00:00\0" \
- "netdev=eth0\0" \
- "bootcmd=run bootcmd_nor\0" \
+ "bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \
+ "cf1=diskboot 200000 0:1\0" \
+ "bootcmd_cf1=run bcf1\0" \
+ "bcf=setenv bootargs root=/dev/hda3\0" \
+ "bootcmd_nfs=run bnfs\0" \
+ "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
+ "panic=1\0" \
+ "bootcmd_nor=cp.b ${kernel_addr} 200000 100000;" \
+ "run norargs addip; run bk\0" \
+ "bnfs=nfs 200000 ${rootpath}/boot/uImage;" \
+ "run nfsargs addip ; run bk\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "try_update=usb start;sleep 2;usb start;sleep 1;" \
+ "fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;" \
+ "source 2F0000\0" \
+ "env_addr=FE060000\0" \
+ "kernel_addr=FE100000\0" \
+ "rootfs_addr=FE200000\0" \
+ "add_mtd=setenv bootargs ${bootargs} mtdparts=" \
+ "phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \
+ "bcf1=run cf1; run bcf; run addip; run bk\0" \
+ "add_consolespec=setenv bootargs ${bootargs} " \
+ "console=/dev/null quiet\0" \
+ "addip=if test -n ${ethaddr};" \
+ "then if test -n ${ipaddr};" \
+ "then setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:"\
+ "${netmask}:${hostname}:${netdev}:off;" \
+ "fi;" \
+ "else;" \
+ "setenv bootargs ${bootargs} no_ethaddr;" \
+ "fi\0" \
+ "hostname=CPUP0\0" \
+ "ethaddr=00:00:00:00:00:00\0" \
+ "netdev=eth0\0" \
+ "bootcmd=run bootcmd_nor\0" \
""
/*
* IPB Bus clocking configuration.
@@ -212,6 +228,7 @@
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START}
+#define CONFIG_SYS_FLASH_BANKS_SIZES {CONFIG_SYS_CS0_SIZE}
/*
* Environment settings
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
index 98b69e3..a0726a9 100644
--- a/include/configs/cerf250.h
+++ b/include/configs/cerf250.h
@@ -38,6 +38,7 @@
#define CONFIG_CERF250 1 /* on Cerf PXA Board */
#define BOARD_LATE_INIT 1
#define CONFIG_BAUDRATE 38400
+#define CONFIG_SYS_TEXT_BASE 0x0
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
@@ -140,15 +141,9 @@
/*
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
@@ -187,6 +182,9 @@
#define CONFIG_SYS_PSSR_VAL 0x20
+#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
+#define CONFIG_SYS_CKEN 0x0
+
/*
* Memory settings
*/
@@ -196,6 +194,8 @@
#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9
#define CONFIG_SYS_MDREFR_VAL 0x03CDC017
#define CONFIG_SYS_MDMRS_VAL 0x00000000
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
/*
* PCMCIA and CF Interfaces
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index 1b129a2..af6769b 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -80,7 +80,9 @@
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
/* List of I2C addresses to be verified by POST */
-#define I2C_ADDR_LIST { CONFIG_SYS_I2C_SLAVE, CONFIG_SYS_I2C_IO, CONFIG_SYS_I2C_EEPROM }
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \
+ CONFIG_SYS_I2C_IO, \
+ CONFIG_SYS_I2C_EEPROM}
/* display image timestamps */
#define CONFIG_TIMESTAMP 1
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index 5f457f8..afc1537 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -39,7 +39,7 @@
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_SYS_GBL_DATA_SIZE 128
-
+#define CONFIG_SYS_TEXT_BASE 0x0
#define CONFIG_ENV_OVERWRITE /* override default environment */
#define CONFIG_BOOTCOMMAND \
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 85147d0..2733fb2 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -213,7 +213,7 @@
#endif
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
diff --git a/include/configs/cradle.h b/include/configs/cradle.h
index d1c1a48..3da3562 100644
--- a/include/configs/cradle.h
+++ b/include/configs/cradle.h
@@ -39,7 +39,7 @@
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
-
+#define CONFIG_SYS_TEXT_BASE 0x0
/*
* Size of malloc() pool
*/
@@ -126,15 +126,9 @@
/*
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
@@ -289,9 +283,9 @@
* Clocks, power control and interrupts
*/
#define CONFIG_SYS_PSSR_VAL 0x00000020
-#define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
-#define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
-#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
+#define CONFIG_SYS_CCCR 0x00000141 /* 100 MHz memory, 200 MHz CPU */
+#define CONFIG_SYS_CKEN 0x00000060 /* FFUART and STUART enabled */
+#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
/* FIXME
*
@@ -319,6 +313,8 @@
#define CONFIG_SYS_MDMRS_VAL 0x00000000
#define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */
#endif
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
/*
* PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
index ae05734..72e47ce 100644
--- a/include/configs/csb226.h
+++ b/include/configs/csb226.h
@@ -45,7 +45,7 @@
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
-
+#define CONFIG_SYS_TEXT_BASE 0x0
/*
* Hardware drivers
*/
@@ -458,6 +458,9 @@
#define CONFIG_SYS_PSSR_VAL 0x20
+#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
+#define CONFIG_SYS_CKEN 0x0
+
/*
* Memory settings
*/
@@ -468,6 +471,8 @@
#define CONFIG_SYS_MDCNFG_VAL 0x09a909a9
#define CONFIG_SYS_MDREFR_VAL 0x038ff030
#define CONFIG_SYS_MDMRS_VAL 0x00220022
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
/*
* PCMCIA and CF Interfaces
diff --git a/include/configs/delta.h b/include/configs/delta.h
deleted file mode 100644
index d53acbf..0000000
--- a/include/configs/delta.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * Configuation settings for the Delta board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
-#define CONFIG_CPU_PXA320
-#define CONFIG_DELTA 1 /* Delta board */
-
-/* #define CONFIG_LCD 1 */
-#ifdef CONFIG_LCD
-#define CONFIG_SHARP_LM8V31
-#endif
-#define BOARD_LATE_INIT 1
-
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-
-/*
- * Hardware drivers
- */
-#undef TURN_ON_ETHERNET
-#ifdef TURN_ON_ETHERNET
-# define CONFIG_DRIVER_SMC91111 1
-# define CONFIG_SMC91111_BASE 0x14000300
-# define CONFIG_SMC91111_EXT_PHY
-# define CONFIG_SMC_USE_32_BIT
-# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
-#endif
-
-#define CONFIG_HARD_I2C 1 /* required for DA9030 access */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE 1 /* I2C controllers address */
-#define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */
-#define CONFIG_SYS_DA9030_EXTON_DELAY 100000 /* wait x us after DA9030 reset via EXTON */
-#define CONFIG_SYS_I2C_INIT_BOARD 1
-/* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */
-
-#define DELTA_CHECK_KEYBD 1 /* check for keys pressed during boot */
-#define CONFIG_PREBOOT "\0"
-
-#ifdef DELTA_CHECK_KEYBD
-# define KEYBD_DATALEN 4 /* we have four keys */
-# define KEYBD_KP_DKIN0 0x1 /* vol+ */
-# define KEYBD_KP_DKIN1 0x2 /* vol- */
-# define KEYBD_KP_DKIN2 0x3 /* multi */
-# define KEYBD_KP_DKIN5 0x4 /* SWKEY_GN */
-#endif /* DELTA_CHECK_KEYBD */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#ifdef TURN_ON_ETHERNET
-
-#define CONFIG_CMD_PING
-
-#else
-
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_I2C
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-
-#endif
-
-/* USB */
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_USB_STORAGE 1
-#define CONFIG_DOS_PARTITION 1
-
-#include <asm/arch/pxa-regs.h> /* for OHCI_REGS_BASE */
-
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE OHCI_REGS_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "delta"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
-
-#define CONFIG_BOOTDELAY -1
-#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
-#define CONFIG_NETMASK 255.255.0.0
-#define CONFIG_IPADDR 192.168.0.21
-#define CONFIG_SERVERIP 192.168.0.250
-#define CONFIG_BOOTCOMMAND "bootm 80000"
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_TIMESTAMP
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER 1
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
-#else
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#endif
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_DEVICE_NULLDEV 1
-
-#define CONFIG_SYS_MEMTEST_START 0x80400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
-
-#define CONFIG_SYS_HZ 1000
-
-/* Monahans Core Frequency */
-#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
-#define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */
-
-
- /* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-#ifdef CONFIG_MMC
-#define CONFIG_PXA_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#endif
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/*
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
-#define PHYS_SDRAM_2 0x81000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
-#define PHYS_SDRAM_3 0x82000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
-#define PHYS_SDRAM_4 0x83000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0x80000000 /* at CS0 */
-#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB Ram */
-
-#undef CONFIG_SYS_SKIP_DRAM_SCRUB
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/*
- * NAND Flash
- */
-#define CONFIG_SYS_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
-#undef CONFIG_SYS_NAND1_BASE
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-
-/* nand timeout values */
-#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000
-#define CONFIG_SYS_NAND_OTHER_TO 100
-#define CONFIG_SYS_NAND_SENDCMD_RETRY 3
-#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
-
-/* NAND Timing Parameters (in ns) */
-#define NAND_TIMING_tCH 10
-#define NAND_TIMING_tCS 0
-#define NAND_TIMING_tWH 20
-#define NAND_TIMING_tWP 40
-
-#define NAND_TIMING_tRH 20
-#define NAND_TIMING_tRP 40
-
-#define NAND_TIMING_tR 11123
-#define NAND_TIMING_tWHR 100
-#define NAND_TIMING_tAR 10
-
-/* NAND debugging */
-#define CONFIG_SYS_DFC_DEBUG1 /* usefull */
-#undef CONFIG_SYS_DFC_DEBUG2 /* noisy */
-#undef CONFIG_SYS_DFC_DEBUG3 /* extremly noisy */
-
-#define CONFIG_MTD_DEBUG
-#define CONFIG_MTD_DEBUG_VERBOSE 1
-
-#define CONFIG_SYS_NO_FLASH 1
-
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_OFFSET 0x40000
-#define CONFIG_ENV_OFFSET_REDUND 0x44000
-#define CONFIG_ENV_SIZE 0x4000
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
index 007cceb..01522cd 100644
--- a/include/configs/innokom.h
+++ b/include/configs/innokom.h
@@ -40,6 +40,8 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* for timer/console/ethernet */
+#define CONFIG_SYS_TEXT_BASE 0x0
+
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
@@ -347,6 +349,9 @@
*/
#define CONFIG_SYS_PSSR_VAL 0x37
+#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
+#define CONFIG_SYS_CKEN 0x0
+
/*
* Memory settings
*
@@ -480,6 +485,9 @@
#define CONFIG_SYS_MCIO0_VAL 0x00000000
#define CONFIG_SYS_MCIO1_VAL 0x00000000
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
+
/*
#define CSB226_USER_LED0 0x00000008
#define CSB226_USER_LED1 0x00000010
diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
index 3a99ec2..62f9691 100644
--- a/include/configs/lubbock.h
+++ b/include/configs/lubbock.h
@@ -43,7 +43,7 @@
#define CONFIG_MMC
#define BOARD_LATE_INIT 1
#define CONFIG_DOS_PARTITION
-
+#define CONFIG_SYS_TEXT_BASE 0x0
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
@@ -202,6 +202,9 @@
#define CONFIG_SYS_PSSR_VAL 0x20
+#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
+#define CONFIG_SYS_CKEN 0x0
+
/*
* Memory settings
*/
@@ -212,6 +215,9 @@
#define CONFIG_SYS_MDREFR_VAL 0x00018018
#define CONFIG_SYS_MDMRS_VAL 0x00000000
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
+
/*
* PCMCIA and CF Interfaces
*/
diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h
index 1062765..9e48857 100644
--- a/include/configs/lwmon.h
+++ b/include/configs/lwmon.h
@@ -349,32 +349,32 @@
/* List of I2C addresses to be verified by POST */
#ifdef CONFIG_USE_FRAM
-#define I2C_ADDR_LIST { /* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
- CONFIG_SYS_I2C_SYSMON_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_POWER_A_ADDR, \
- CONFIG_SYS_I2C_POWER_B_ADDR, \
- CONFIG_SYS_I2C_KEYBD_ADDR, \
- CONFIG_SYS_I2C_PICIO_ADDR, \
- CONFIG_SYS_I2C_EEPROM_ADDR, \
- }
+#define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
+ CONFIG_SYS_I2C_SYSMON_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR, \
+ CONFIG_SYS_I2C_POWER_A_ADDR, \
+ CONFIG_SYS_I2C_POWER_B_ADDR, \
+ CONFIG_SYS_I2C_KEYBD_ADDR, \
+ CONFIG_SYS_I2C_PICIO_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_ADDR, \
+ }
#else /* Use EEPROM - which show up on 8 consequtive addresses */
-#define I2C_ADDR_LIST { /* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
- CONFIG_SYS_I2C_SYSMON_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_POWER_A_ADDR, \
- CONFIG_SYS_I2C_POWER_B_ADDR, \
- CONFIG_SYS_I2C_KEYBD_ADDR, \
- CONFIG_SYS_I2C_PICIO_ADDR, \
- CONFIG_SYS_I2C_EEPROM_ADDR+0, \
- CONFIG_SYS_I2C_EEPROM_ADDR+1, \
- CONFIG_SYS_I2C_EEPROM_ADDR+2, \
- CONFIG_SYS_I2C_EEPROM_ADDR+3, \
- CONFIG_SYS_I2C_EEPROM_ADDR+4, \
- CONFIG_SYS_I2C_EEPROM_ADDR+5, \
- CONFIG_SYS_I2C_EEPROM_ADDR+6, \
- CONFIG_SYS_I2C_EEPROM_ADDR+7, \
- }
+#define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
+ CONFIG_SYS_I2C_SYSMON_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR, \
+ CONFIG_SYS_I2C_POWER_A_ADDR, \
+ CONFIG_SYS_I2C_POWER_B_ADDR, \
+ CONFIG_SYS_I2C_KEYBD_ADDR, \
+ CONFIG_SYS_I2C_PICIO_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+0, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+1, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+2, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+3, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+4, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+5, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+6, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+7, \
+ }
#endif /* CONFIG_USE_FRAM */
/*-----------------------------------------------------------------------
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index a4e92cc..63e22d4 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -306,14 +306,13 @@
#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
-#define I2C_ADDR_LIST { \
- CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_EEPROM_CPU_ADDR, \
- CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
- CONFIG_SYS_I2C_DSPIC_ADDR, \
- CONFIG_SYS_I2C_DSPIC_2_ADDR, \
- CONFIG_SYS_I2C_DSPIC_KEYB_ADDR, \
- CONFIG_SYS_I2C_DSPIC_IO_ADDR }
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
+ CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
+ CONFIG_SYS_I2C_DSPIC_ADDR, \
+ CONFIG_SYS_I2C_DSPIC_2_ADDR, \
+ CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
+ CONFIG_SYS_I2C_DSPIC_IO_ADDR }
/*
* Pass open firmware flat tree
diff --git a/include/configs/palmld.h b/include/configs/palmld.h
index 926728b..a2310a9 100644
--- a/include/configs/palmld.h
+++ b/include/configs/palmld.h
@@ -34,6 +34,7 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_MALLOC_LEN (128*1024)
#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_SYS_TEXT_BASE 0x0
#define CONFIG_BOOTCOMMAND \
"if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then " \
diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h
index fe87648..40ab0bf 100644
--- a/include/configs/palmtc.h
+++ b/include/configs/palmtc.h
@@ -36,6 +36,7 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_MALLOC_LEN (128*1024)
#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_SYS_TEXT_BASE 0x0
#define CONFIG_BOOTCOMMAND \
"if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h
index 3b6e60a..b366f38 100644
--- a/include/configs/pleb2.h
+++ b/include/configs/pleb2.h
@@ -39,6 +39,7 @@
#undef CONFIG_LCD
#undef CONFIG_MMC
#define BOARD_LATE_INIT 1
+#define CONFIG_SYS_TEXT_BASE 0x0
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
@@ -155,15 +156,9 @@
/*
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
@@ -213,9 +208,9 @@
#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
#define CONFIG_SYS_PSSR_VAL 0x20
-#define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
-#define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
-#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
+#define CONFIG_SYS_CCCR 0x00000141 /* 100 MHz memory, 200 MHz CPU */
+#define CONFIG_SYS_CKEN 0x00000060 /* FFUART and STUART enabled */
+#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
/*
* Memory settings
@@ -231,6 +226,9 @@
/* bits set in lowlevel_init.S */
#define CONFIG_SYS_MDMRS_VAL 0x00000000
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
+
/*
* PCMCIA and CF Interfaces
*/
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index 4581674..b4327c6 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -43,6 +43,7 @@
*/
#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */
#undef CONFIG_SKIP_RELOCATE_UBOOT /* define for developing */
+#define CONFIG_SYS_TEXT_BASE 0x0
/*
* define the following to enable debug blinks. A debug blink function
@@ -271,7 +272,7 @@
/*
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
@@ -317,6 +318,9 @@
#define CONFIG_SYS_PSSR_VAL 0x20
+#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
+#define CONFIG_SYS_CKEN 0x0
+
/*
* Memory settings
*/
@@ -326,6 +330,8 @@
#define CONFIG_SYS_MDCNFG_VAL 0x090009C9
#define CONFIG_SYS_MDREFR_VAL 0x0085C017
#define CONFIG_SYS_MDMRS_VAL 0x00220022
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
/*
* PCMCIA and CF Interfaces
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index 2c18e2f..6627f99 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -62,8 +62,10 @@
/* MEMORY */
#if defined(CONFIG_SH_32BIT)
-#define SH7785LCR_SDRAM_PHYS_BASE (0x48000000)
-#define SH7785LCR_SDRAM_BASE (0x88000000)
+/* 0x40000000 - 0x47FFFFFF does not use */
+#define CONFIG_SH_SDRAM_OFFSET (0x8000000)
+#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
+#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index b5ac168..880c8a3 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -271,10 +271,10 @@
/* List of I2C addresses to be verified by POST */
#if defined (CONFIG_MINIFAP)
-#undef I2C_ADDR_LIST
-#define I2C_ADDR_LIST { CONFIG_SYS_I2C_EEPROM_ADDR, \
- CONFIG_SYS_I2C_HWMON_ADDR, \
- CONFIG_SYS_I2C_SLAVE }
+#undef CONFIG_SYS_POST_I2C_ADDRS
+#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_HWMON_ADDR, \
+ CONFIG_SYS_I2C_SLAVE}
#endif
/*
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index 4743495..ac3566c 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -44,6 +44,7 @@
#define CONFIG_MMC 1
#define BOARD_LATE_INIT 1
+#define CONFIG_SYS_TEXT_BASE 0x0
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
diff --git a/include/configs/vision2.h b/include/configs/vision2.h
index a2ecbe5..d2d9565 100644
--- a/include/configs/vision2.h
+++ b/include/configs/vision2.h
@@ -211,4 +211,18 @@
#define CONFIG_SYS_NO_FLASH
+/*
+ * Framebuffer and LCD
+ */
+#define CONFIG_PREBOOT
+#define CONFIG_LCD
+#define CONFIG_VIDEO_MX5
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+
#endif /* __CONFIG_H */
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
index c9d9c69..3107014 100644
--- a/include/configs/vpac270.h
+++ b/include/configs/vpac270.h
@@ -27,6 +27,7 @@
*/
#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
#define CONFIG_VPAC270 1 /* Voipac PXA270 board */
+#define CONFIG_SYS_TEXT_BASE 0x0
/*
* Environment settings
diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h
deleted file mode 100644
index a961a27..0000000
--- a/include/configs/wepep250.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Copyright (C) 2003 ETC s.r.o.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Written by Peter Figuli <peposh@etc.sk>, 2003.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PXA250 1 /* this is an PXA250 CPU */
-#define CONFIG_WEPEP250 1 /* config for wepep250 board */
-#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
-
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
-
-/*
- * Select serial console configuration
- */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_BTUART 1 /* BTUART is default on WEP dev board */
-#define CONFIG_BAUDRATE 115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_SOURCE
-
-
-/*
- * Boot options. Setting delay to -1 stops autostart count down.
- * NOTE: Sending parameters to kernel depends on kernel version and
- * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
- * parameters at all! Do not get confused by them so.
- */
-#define CONFIG_BOOTDELAY -1
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=32m console=ttyS01,115200n8"
-#define CONFIG_BOOTCOMMAND "bootm 40000"
-
-
-/*
- * General options for u-boot. Modify to save memory foot print
- */
-#define CONFIG_SYS_LONGHELP /* undef saves memory */
-#define CONFIG_SYS_PROMPT "WEP> " /* prompt string */
-#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
-#define CONFIG_SYS_MAXARGS 16 /* max command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
-
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest test area */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000
-
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Definitions related to passing arguments to kernel.
- */
-#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
-#undef CONFIG_INITRD_TAG /* do not send initrd params */
-#undef CONFIG_VFD /* do not send framebuffer setup */
-
-
-/*
- * Malloc pool need to host env + 128 Kb reserve for other allocations.
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-
-#define CONFIG_STACKSIZE (120<<10) /* stack size */
-
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
-#endif
-
-/*
- * SDRAM Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
-#define WEP_SDRAM_1 0xa0000000 /* SDRAM bank #1 */
-#define WEP_SDRAM_1_SIZE 0x02000000 /* 32 MB ( 2 chip ) */
-#define WEP_SDRAM_2 0xa2000000 /* SDRAM bank #2 */
-#define WEP_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define WEP_SDRAM_3 0xa8000000 /* SDRAM bank #3 */
-#define WEP_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define WEP_SDRAM_4 0xac000000 /* SDRAM bank #4 */
-#define WEP_SDRAM_4_SIZE 0x00000000 /* 0 MB */
-
-#define CONFIG_SYS_DRAM_BASE 0xa0000000
-#define CONFIG_SYS_DRAM_SIZE 0x02000000
-
-/* Uncomment used SDRAM chip */
-#define WEP_SDRAM_K4S281633
-/*#define WEP_SDRAM_K4S561633*/
-
-
-/*
- * Configuration for FLASH memory
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
-#define WEP_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */
-#define WEP_FLASH_INTERLEAVE 2 /* ... made of 2 chips */
-#define WEP_FLASH_BANK_SIZE 0x2000000 /* size of one flash bank*/
-#define WEP_FLASH_SECT_SIZE 0x0040000 /* size of erase sector */
-#define WEP_FLASH_BASE 0x0000000 /* location of flash memory */
-#define WEP_FLASH_UNLOCK 1 /* perform hw unlock first */
-
-
-/* This should be defined if CFI FLASH device is present. Actually benefit
- is not so clear to me. In other words we can provide more informations
- to user, but this expects more complex flash handling we do not provide
- now.*/
-#undef CONFIG_SYS_FLASH_CFI
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */
-
-#define CONFIG_SYS_FLASH_BASE WEP_FLASH_BASE
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * Right now there is no gain for user, but later on booting kernel might be
- * possible. Consider using XIP kernel running from flash to save RAM
- * footprint.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 5
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
-/*
- * Environment setup. Definitions of monitor location and size with
- * definition of environment setup ends up in 2 possibilities.
- * 1. Embeded environment - in u-boot code is space for environment
- * 2. Environment is read from predefined sector of flash
- * Right now we support 2. possiblity, but expecting no env placed
- * on mentioned address right now. This also needs to provide whole
- * sector for it - for us 256Kb is really waste of memory. U-boot uses
- * default env. and until kernel parameters could be sent to kernel
- * env. has no sense to us.
- */
-
-#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128kb ( 1 flash sector ) */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR 0x20000 /* absolute address for now */
-#define CONFIG_ENV_SIZE 0x2000
-
-#define PHYS_SDRAM_1 WEP_SDRAM_1
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-#undef CONFIG_ENV_OVERWRITE /* env is not writable now */
-
-/*
- * Well this has to be defined, but on the other hand it is used differently
- * one may expect. For instance loadb command do not cares :-)
- * So advice is - do not relay on this...
- */
-#define CONFIG_SYS_LOAD_ADDR 0x40000
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 67d4106..18b68fa 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -42,6 +42,7 @@
*/
#define CONFIG_PXA250 1 /* This is an PXA255 CPU */
#define CONFIG_XAENIAX 1 /* on a xaeniax board */
+#define CONFIG_SYS_TEXT_BASE 0x0
#define BOARD_LATE_INIT 1
@@ -437,8 +438,9 @@
*/
#define CONFIG_SYS_PSSR_VAL 0x00000030
-#define CONFIG_SYS_CKEN_VAL 0x00000080 /* */
-#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
+#define CONFIG_SYS_CKEN 0x00000080 /* */
+#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
+#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
/*
@@ -562,6 +564,9 @@
*/
#define CONFIG_SYS_MDMRS_VAL 0x00320032
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
+
/*
* PCMCIA and CF Interfaces
*/
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index 2ff9a28..ea52454 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -35,6 +35,7 @@
#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
#define CONFIG_XM250 1 /* on a MicroSys XM250 Board */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_SYS_TEXT_BASE 0x0
/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_NO_DCACHE
@@ -322,9 +323,9 @@
* Clocks, power control and interrupts
*/
#define CONFIG_SYS_PSSR_VAL 0x00000030
-#define CONFIG_SYS_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */
-#define CONFIG_SYS_CKEN_VAL 0x000141ec /* FFUART and STUART enabled */
-#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
+#define CONFIG_SYS_CCCR 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */
+#define CONFIG_SYS_CKEN 0x000141ec /* FFUART and STUART enabled */
+#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
/* FIXME
*
@@ -343,6 +344,8 @@
#define CONFIG_SYS_MDCNFG_VAL 0x000009c9
#define CONFIG_SYS_MDMRS_VAL 0x00220022
#define CONFIG_SYS_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
/*
* PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
diff --git a/include/configs/XPEDITE1000.h b/include/configs/xpedite1000.h
index 5605849..d0f9363 100644
--- a/include/configs/XPEDITE1000.h
+++ b/include/configs/xpedite1000.h
@@ -33,6 +33,7 @@
/* High Level Configuration Options */
#define CONFIG_XPEDITE1000 1
#define CONFIG_SYS_BOARD_NAME "XPedite1000"
+#define CONFIG_SYS_FORM_PMC 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1
#define CONFIG_440GX 1 /* 440 GX */
@@ -341,8 +342,8 @@ extern void out32(unsigned int, unsigned long);
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
- "osfile=/home/user/uImage-XPedite1000\0" \
- "fdtfile=/home/user/xpedite1000.dtb\0" \
+ "osfile=/home/user/board.uImage\0" \
+ "fdtfile=/home/user/board.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \
diff --git a/include/configs/XPEDITE5170.h b/include/configs/xpedite517x.h
index 1851997..8df9edd 100644
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/xpedite517x.h
@@ -22,7 +22,7 @@
*/
/*
- * xpedite5170 board configuration file
+ * xpedite517x board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
@@ -34,6 +34,7 @@
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
#define CONFIG_SYS_BOARD_NAME "XPedite5170"
+#define CONFIG_SYS_FORM_3U_VPX 1
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
@@ -107,6 +108,21 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
+ CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
+ CONFIG_SYS_I2C_DS4510_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_LM90_ADDR, \
+ CONFIG_SYS_I2C_PCA9553_ADDR, \
+ CONFIG_SYS_I2C_PCA953X_ADDR0, \
+ CONFIG_SYS_I2C_PCA953X_ADDR1, \
+ CONFIG_SYS_I2C_PCA953X_ADDR2, \
+ CONFIG_SYS_I2C_PCA953X_ADDR3, \
+ CONFIG_SYS_I2C_PEX8518_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR}
+/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
+#define I2C_ADDR_IGNORE_LIST {0x50}
/*
* Memory map
@@ -258,6 +274,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
#define CONFIG_DTT_DS1621
#define CONFIG_DTT_SENSORS { 0 }
+#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
/* I2C EEPROM - AT24C128B */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
@@ -281,6 +298,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
+#define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
/*
* PU = pulled high, PD = pulled low
@@ -324,18 +342,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* PCIE1 - PEX8518 */
-#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
/* PCIE2 - VPX P1 */
-#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
@@ -545,6 +563,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
@@ -725,8 +744,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
- "osfile=/home/user/uImage-XPedite5170\0" \
- "fdtfile=/home/user/xpedite5170.dtb\0" \
+ "osfile=/home/user/board.uImage\0" \
+ "fdtfile=/home/user/board.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \
diff --git a/include/configs/XPEDITE5200.h b/include/configs/xpedite520x.h
index d0e9492..2f31337 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/xpedite520x.h
@@ -22,7 +22,7 @@
*/
/*
- * xpedite5200 board configuration file
+ * xpedite520x board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
@@ -36,6 +36,7 @@
#define CONFIG_MPC8548 1
#define CONFIG_XPEDITE5200 1
#define CONFIG_SYS_BOARD_NAME "XPedite5200"
+#define CONFIG_SYS_FORM_PMC_XMC 1
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#ifndef CONFIG_SYS_TEXT_BASE
@@ -92,6 +93,13 @@
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
+ CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_PCA953X_ADDR0, \
+ CONFIG_SYS_I2C_PCA953X_ADDR1, \
+ CONFIG_SYS_I2C_RTC_ADDR}
/*
* Memory map
@@ -250,7 +258,7 @@
#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
-#define CONFIG_SYS_PCA953X_FLASH_WP 0x20
+#define CONFIG_SYS_PCA953X_NVM_WP 0x20
#define CONFIG_SYS_PCA953X_MONARCH 0x40
#define CONFIG_SYS_PCA953X_EREADY 0x80
@@ -264,14 +272,17 @@
#define CONFIG_SYS_PCA953X_P14_IO6 0x40
#define CONFIG_SYS_PCA953X_P14_IO7 0x80
+/* 12-bit ADC used to measure CPU diode */
+#define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
+
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
@@ -339,6 +350,7 @@
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_REGINFO
@@ -521,8 +533,8 @@
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
- "osfile=/home/user/uImage-XPedite5200\0" \
- "fdtfile=/home/user/xpedite5200.dtb\0" \
+ "osfile=/home/user/board.uImage\0" \
+ "fdtfile=/home/user/board.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \
diff --git a/include/configs/XPEDITE5370.h b/include/configs/xpedite537x.h
index 629dc0d..e7de13a 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/xpedite537x.h
@@ -22,7 +22,7 @@
*/
/*
- * xpedite5370 board configuration file
+ * xpedite537x board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
@@ -36,6 +36,7 @@
#define CONFIG_MPC8572 1
#define CONFIG_XPEDITE5370 1
#define CONFIG_SYS_BOARD_NAME "XPedite5370"
+#define CONFIG_SYS_FORM_3U_VPX 1
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#ifndef CONFIG_SYS_TEXT_BASE
@@ -110,6 +111,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
+ CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
+ CONFIG_SYS_I2C_DS4510_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_LM90_ADDR, \
+ CONFIG_SYS_I2C_PCA953X_ADDR0, \
+ CONFIG_SYS_I2C_PCA953X_ADDR1, \
+ CONFIG_SYS_I2C_PCA953X_ADDR2, \
+ CONFIG_SYS_I2C_PCA953X_ADDR3, \
+ CONFIG_SYS_I2C_PEX8518_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR}
+/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
+#define I2C_ADDR_IGNORE_LIST {0x50}
/*
* Memory map
@@ -265,6 +280,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
#define CONFIG_DTT_DS1621
#define CONFIG_DTT_SENSORS { 0 }
+#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
/* I2C EEPROM - AT24C128B */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
@@ -334,18 +350,18 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* PCIE1 - VPX P1 */
-#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
/* PCIE2 - PEX8518 */
-#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
@@ -396,6 +412,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SNTP
@@ -578,8 +595,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
- "osfile=/home/user/uImage-XPedite5370\0" \
- "fdtfile=/home/user/xpedite5370.dtb\0" \
+ "osfile=/home/user/board.uImage\0" \
+ "fdtfile=/home/user/board.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
new file mode 100644
index 0000000..a849cf9
--- /dev/null
+++ b/include/configs/xpedite550x.h
@@ -0,0 +1,607 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * xpedite550x board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
+#define CONFIG_P2020 1
+#define CONFIG_XPEDITE550X 1
+#define CONFIG_SYS_BOARD_NAME "XPedite5500"
+#define CONFIG_SYS_FORM_PMC_XMC 1
+#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
+#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+#endif
+
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#define CONFIG_PCIE1 1 /* PCIE controler 1 (PEX8112 or XMC) */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+#define CONFIG_FSL_ELBC 1
+
+/*
+ * Multicore config
+ */
+#define CONFIG_MP
+#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
+#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
+
+/*
+ * DDR config
+ */
+#define CONFIG_FSL_DDR3
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#define SPD_EEPROM_ADDRESS1 0x54
+#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x20000000
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
+ CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
+ CONFIG_SYS_I2C_LM75_ADDR, \
+ CONFIG_SYS_I2C_LM90_ADDR, \
+ CONFIG_SYS_I2C_PCA953X_ADDR0, \
+ CONFIG_SYS_I2C_PCA953X_ADDR2, \
+ CONFIG_SYS_I2C_PCA953X_ADDR3, \
+ CONFIG_SYS_I2C_RTC_ADDR}
+
+/*
+ * Memory map
+ * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
+ * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
+ * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
+ * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
+ * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
+ * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
+ * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
+ * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
+ * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE 0xef800000
+#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
+#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
+ CONFIG_SYS_NAND_BASE2}
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
+#define CONFIG_NAND_FSL_ELBC
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE 0xf8000000
+#define CONFIG_SYS_FLASH_BASE2 0xf0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
+ {0xf7f40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
+ BR_PS_16 | \
+ BR_V)
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
+ OR_GPCM_CSNT | \
+ OR_GPCM_XACS | \
+ OR_GPCM_ACS_DIV2 | \
+ OR_GPCM_SCY_8 | \
+ OR_GPCM_TRLX | \
+ OR_GPCM_EHTR | \
+ OR_GPCM_EAD)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
+ BR_PS_16 | \
+ BR_V)
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
+ (2<<BR_DECC_SHIFT) | \
+ BR_PS_8 | \
+ BR_MS_FCM | \
+ BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
+ OR_FCM_PGS | \
+ OR_FCM_CSCT | \
+ OR_FCM_CST | \
+ OR_FCM_CHT | \
+ OR_FCM_SCY_1 | \
+ OR_FCM_TRLX | \
+ OR_FCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
+ (2<<BR_DECC_SHIFT) | \
+ BR_PS_8 | \
+ BR_MS_FCM | \
+ BR_V)
+#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
+#define CONFIG_SYS_INIT_RAM_END 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+#define CONFIG_FDT_FIXUP_PCI_IRQ 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_I2C_MULTI_BUS
+
+/* I2C DS7505 temperature sensor */
+#define CONFIG_DTT_LM75
+#define CONFIG_DTT_SENSORS { 0 }
+#define CONFIG_SYS_I2C_LM75_ADDR 0x48
+
+/* I2C ADT7461 temperature sensor */
+#define CONFIG_SYS_I2C_LM90_ADDR 0x4C
+
+/* I2C EEPROM - AT24C128B */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
+#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
+#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
+#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/*
+ * GPIO pin definitions, PU = pulled high, PD = pulled low
+ */
+/* PCA9557 @ 0x18*/
+#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
+#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
+#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
+#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
+
+/* PCA9557 @ 0x1e*/
+#define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
+#define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
+#define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
+
+/* PCA9557 @ 0x1f */
+#define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1 - PEX8112 or XMC, depending on build option */
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
+
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_TSEC_TBI
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_ETHPRIME "eTSEC2"
+
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHY_ADDR 2
+#define TSEC2_PHYIDX 0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_PHY_ADDR 3
+#define TSEC3_PHYIDX 0
+#define CONFIG_HAS_ETH2
+
+/*
+ * USB
+ */
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_PREBOOT /* enable preboot variable */
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE 0x8000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff Pri FDT (256KB)
+ * fef00000 - ffefffff Pri OS image (16MB)
+ * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
+ *
+ * f7f80000 - f7ffffff Sec U-Boot (512 KB)
+ * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
+ * f7f00000 - f7f3ffff Sec FDT (256KB)
+ * f6f00000 - f7efffff Sec OS image (16MB)
+ * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
+
+#define CONFIG_PROG_UBOOT1 \
+ "$download_cmd $loadaddr $ubootfile; " \
+ "if test $? -eq 0; then " \
+ "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
+ "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
+ "if test $? -ne 0; then " \
+ "echo PROGRAM FAILED; " \
+ "else; " \
+ "echo PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_UBOOT2 \
+ "$download_cmd $loadaddr $ubootfile; " \
+ "if test $? -eq 0; then " \
+ "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
+ "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
+ "if test $? -ne 0; then " \
+ "echo PROGRAM FAILED; " \
+ "else; " \
+ "echo PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_BOOT_OS_NET \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "if test -n $fdtaddr; then " \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "bootm $osaddr - $fdtaddr; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi; " \
+ "else; " \
+ "bootm $osaddr; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_OS1 \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
+ "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
+ "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo OS PROGRAM FAILED; " \
+ "else; " \
+ "echo OS PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_OS2 \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
+ "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
+ "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo OS PROGRAM FAILED; " \
+ "else; " \
+ "echo OS PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_FDT1 \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
+ "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
+ "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo FDT PROGRAM FAILED; " \
+ "else; " \
+ "echo FDT PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_FDT2 \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
+ "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
+ "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo FDT PROGRAM FAILED; " \
+ "else; " \
+ "echo FDT PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=yes\0" \
+ "download_cmd=tftp\0" \
+ "console_args=console=ttyS0,115200\0" \
+ "root_args=root=/dev/nfs rw\0" \
+ "misc_args=ip=on\0" \
+ "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+ "bootfile=/home/user/file\0" \
+ "osfile=/home/user/board.uImage\0" \
+ "fdtfile=/home/user/board.dtb\0" \
+ "ubootfile=/home/user/u-boot.bin\0" \
+ "fdtaddr=c00000\0" \
+ "osaddr=0x1000000\0" \
+ "loadaddr=0x1000000\0" \
+ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
+ "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
+ "prog_os1="CONFIG_PROG_OS1"\0" \
+ "prog_os2="CONFIG_PROG_OS2"\0" \
+ "prog_fdt1="CONFIG_PROG_FDT1"\0" \
+ "prog_fdt2="CONFIG_PROG_FDT2"\0" \
+ "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
+ "bootcmd_flash1=run set_bootargs; " \
+ "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+ "bootcmd_flash2=run set_bootargs; " \
+ "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+ "bootcmd=run bootcmd_flash1\0"
+#endif /* __CONFIG_H */
diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h
deleted file mode 100644
index 9606b53..0000000
--- a/include/configs/xsengine.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
-#define CONFIG_XSENGINE 1
-#define CONFIG_MMC 1
-#define CONFIG_DOS_PARTITION 1
-#define BOARD_LATE_INIT 1
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
-
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
-
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
-#define CONFIG_SYS_DRAM_BASE 0xa0000000
-#define CONFIG_SYS_DRAM_SIZE 0x04000000
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
-
-/* FLASH organization */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0x00000000 /* Flash Bank #2 */
-#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 127 KB sectors */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=xsengine-0"
-#define MTDPARTS_DEFAULT "mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)"
-*/
-
-/* Environment settings */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector (after monitor)*/
-#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Size of the Environment Sector */
-#define CONFIG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (75*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (50*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-
-/* Hardware drivers */
-#define CONFIG_NET_MULTI
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE 0x04000300
-#define CONFIG_SMC_USE_32_BIT 1
-
-/* select serial console configuration */
-#define CONFIG_PXA_SERIAL
-#define CONFIG_FFUART 1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_BAUDRATE 115200
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_JFFS2
-
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.1.50
-#define CONFIG_SERVERIP 192.168.1.2
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
-#define CONFIG_CMDLINE_TAG
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_HUSH_PARSER 1
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_MEMTEST_START 0xA0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
-#define CONFIG_SYS_LOAD_ADDR 0xA0000000 /* load kernel to this address */
-
-#ifdef CONFIG_MMC
-#define CONFIG_PXA_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_BASE 0xF0000000
-#endif
-
-/* Stack sizes - The stack sizes are set up in start.S using the settings below */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
-#endif
-
-/* GP set register */
-#define CONFIG_SYS_GPSR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
-#define CONFIG_SYS_GPSR1_VAL 0x00020000 /* nPWE */
-#define CONFIG_SYS_GPSR2_VAL 0x0000C000 /* CS2, CS3 */
-
-/* GP clear register */
-#define CONFIG_SYS_GPCR0_VAL 0x00000000
-#define CONFIG_SYS_GPCR1_VAL 0x00000000
-#define CONFIG_SYS_GPCR2_VAL 0x00000000
-
-/* GP direction register */
-#define CONFIG_SYS_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
-#define CONFIG_SYS_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */
-#define CONFIG_SYS_GPDR2_VAL 0x0000C000 /* CS2, CS3 */
-
-/* GP rising edge detect register */
-#define CONFIG_SYS_GRER0_VAL 0x00000000
-#define CONFIG_SYS_GRER1_VAL 0x00000000
-#define CONFIG_SYS_GRER2_VAL 0x00000000
-
-/* GP falling edge detect register */
-#define CONFIG_SYS_GFER0_VAL 0x00000000
-#define CONFIG_SYS_GFER1_VAL 0x00000000
-#define CONFIG_SYS_GFER2_VAL 0x00000000
-
-/* GP alternate function register */
-#define CONFIG_SYS_GAFR0_L_VAL 0x80000000 /* CS1 */
-#define CONFIG_SYS_GAFR0_U_VAL 0x00000010 /* RDY */
-#define CONFIG_SYS_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */
-#define CONFIG_SYS_GAFR1_U_VAL 0x00000008 /* nPWE */
-#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */
-#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
-
-#define CONFIG_SYS_PSSR_VAL 0x00000020 /* Power manager sleep status */
-#define CONFIG_SYS_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU */
-#define CONFIG_SYS_CKEN_VAL 0x000000C0 /* BTUART and FFUART enabled */
-#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
-
-/* Memory settings */
-#define CONFIG_SYS_MSC0_VAL 0x25F425F0
-
-/* MDCNFG: SDRAM Configuration Register */
-#define CONFIG_SYS_MDCNFG_VAL 0x000009C9
-
-/* MDREFR: SDRAM Refresh Control Register */
-#define CONFIG_SYS_MDREFR_VAL 0x00018018
-
-/* MDMRS: Mode Register Set Configuration Register */
-#define CONFIG_SYS_MDMRS_VAL 0x00220022
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index ce65d1f..48537e3 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -27,6 +27,7 @@
*/
#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */
+#define CONFIG_SYS_TEXT_BASE 0x0
#undef BOARD_LATE_INIT
#undef CONFIG_SKIP_RELOCATE_UBOOT