diff options
author | Tom Rini <trini@konsulko.com> | 2016-11-29 19:42:48 -0500 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2016-11-29 19:42:48 -0500 |
commit | 6b29a395b62965eef6b5065d3a526a8588a92038 (patch) | |
tree | d9404d155aa96dd58ff9d02cdb2a30e7136405da /include/configs | |
parent | dbd5df89d65172f94dec78af809f1e50dbd61fe6 (diff) | |
parent | e8a390f0189c5868f2fa305004821bcfcd71d32c (diff) | |
download | u-boot-imx-6b29a395b62965eef6b5065d3a526a8588a92038.zip u-boot-imx-6b29a395b62965eef6b5065d3a526a8588a92038.tar.gz u-boot-imx-6b29a395b62965eef6b5065d3a526a8588a92038.tar.bz2 |
Merge git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'include/configs')
45 files changed, 90 insertions, 179 deletions
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 5f8b99e..cd4333f 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -10,8 +10,6 @@ /* * B4860 QDS board configuration file */ -#define CONFIG_B4860QDS - #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg @@ -75,7 +73,7 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#ifndef CONFIG_PPC_B4420 +#ifndef CONFIG_ARCH_B4420 #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ @@ -790,7 +788,7 @@ unsigned long get_board_ddr_clk(void); #define __USB_PHY_TYPE ulpi -#ifdef CONFIG_PPC_B4860 +#ifdef CONFIG_ARCH_B4860 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ "bank_intlv=cs0_cs1;" \ "en_cpc:cpc2;" diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 86419eb..aaf7106 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -11,10 +11,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_BSC9131RDB -#define CONFIG_BSC9131 #define CONFIG_NAND_FSL_IFC -#endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 0e0eefb..8eee738 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -11,10 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_BSC9132QDS -#define CONFIG_BSC9132 -#endif - #define CONFIG_MISC_INIT_R #ifdef CONFIG_SDCARD diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 41dde82..39eefb4 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -11,10 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_C29XPCIE -#define CONFIG_PPC_C29X -#endif - #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_SYS_TEXT_BASE 0x11000000 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 0f29863..446303d 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -40,8 +40,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8536 1 -#define CONFIG_MPC8536DS 1 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index af3e85e..54932fd 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -21,8 +21,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8540 1 /* MPC8540 specific */ -#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ /* * default CCARBAR is at 0xff700000 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 134add5..29bca4c 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -17,8 +17,6 @@ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_MPC8541 1 /* MPC8541 specific */ -#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index d868ce2..6c17a3b 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -14,8 +14,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8544 1 -#define CONFIG_MPC8544DS 1 #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index fa114b3..310c070 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -16,8 +16,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8548 1 /* MPC8548 specific */ -#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 908b7ed..3cf8d97 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -17,8 +17,6 @@ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_MPC8555 1 /* MPC8555 specific */ -#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 25227e5..641521c 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -22,8 +22,6 @@ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ -#define CONFIG_MPC8560 1 /* * default CCARBAR is at 0xff700000 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 62f06db..e7adb17 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -13,8 +13,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8568 1 /* MPC8568 specific */ -#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index a2ec52b..91f0104 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -13,8 +13,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8569 1 /* MPC8569 specific */ -#define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index d4be140..e134560 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -28,8 +28,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8572 1 -#define CONFIG_MPC8572DS 1 #define CONFIG_MP 1 /* support multiple processors */ #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 2529d8a..75693a0 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -12,8 +12,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_MPC8610 1 /* MPC8610 specific */ -#define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #define CONFIG_SYS_TEXT_BASE 0xfff00000 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index b35bbd4..c94b329 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -17,8 +17,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_MPC8641 1 /* MPC8641 specific */ -#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ #define CONFIG_MP 1 /* support multiple processors */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #define CONFIG_ADDR_MAP 1 /* Use addr map */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index c45b091..3ced88d 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -11,7 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_P1010 #define CONFIG_E500 /* BOOKE e500 family */ #include <asm/config_mpc85xx.h> #define CONFIG_NAND_FSL_IFC @@ -175,9 +174,9 @@ #endif /* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" #endif #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 @@ -379,7 +378,7 @@ extern unsigned long get_sdram_size(void); | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ @@ -389,7 +388,7 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ @@ -405,7 +404,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) /* NAND Flash Timing Params */ #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0C) | \ @@ -420,7 +419,7 @@ extern unsigned long get_sdram_size(void); FTIM2_NAND_TWHRE(0x0f) #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ /* ONFI NAND Flash mode0 Timing Params */ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ @@ -593,7 +592,7 @@ extern unsigned long get_sdram_size(void); #define I2C_PCA9557_BUS_NUM 0 /* I2C EEPROM */ -#if defined(CONFIG_P1010RDB_PB) +#if defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_ID_EEPROM #ifdef CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID @@ -719,10 +718,10 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) #else -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ #endif @@ -843,7 +842,7 @@ extern unsigned long get_sdram_size(void); "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ CONFIG_BOOTMODE -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_BOOTMODE \ "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ @@ -852,7 +851,7 @@ extern unsigned long get_sdram_size(void); "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_BOOTMODE \ "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 6a4937b..6f07080 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -90,8 +90,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_P1022 -#define CONFIG_P1022DS #define CONFIG_MP /* support multiple processors */ #ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index eba66ec..5061286 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -25,7 +25,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_P1023 #define CONFIG_MP /* support multiple processors */ #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 350756b..417bfd3 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -11,9 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_P2041RDB -#define CONFIG_PPC_P2041 - #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index c901fe2..52ef432 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -8,9 +8,6 @@ * P3041 DS board configuration file * */ -#define CONFIG_P3041DS -#define CONFIG_PPC_P3041 - #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ #define CONFIG_MMC diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 0d44c00..65ec8f7 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -8,9 +8,6 @@ * P4080 DS board configuration file * Also supports P4040 DS */ -#define CONFIG_P4080DS -#define CONFIG_PPC_P4080 - #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ #define CONFIG_MMC diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index d2cedfe..17e941e 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -8,9 +8,6 @@ * P5020 DS board configuration file * Also supports P5010 DS */ -#define CONFIG_P5020DS -#define CONFIG_PPC_P5020 - #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ #define CONFIG_MMC diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h index dc82721..078e60c 100644 --- a/include/configs/P5040DS.h +++ b/include/configs/P5040DS.h @@ -8,9 +8,6 @@ * P5040 DS board configuration file * */ -#define CONFIG_P5040DS -#define CONFIG_PPC_P5040 - #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ #define CONFIG_MMC diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index c290101..3c0a0c9 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -497,7 +497,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* Video */ -#ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ +#ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ #define CONFIG_FSL_DIU_FB #ifdef CONFIG_FSL_DIU_FB #define CONFIG_FSL_DIU_CH7301 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 5b233bc..e2aea8b 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -34,7 +34,7 @@ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ /* support deep sleep */ -#ifdef CONFIG_PPC_T1024 +#ifdef CONFIG_ARCH_T1024 #define CONFIG_DEEP_SLEEP #endif #if defined(CONFIG_DEEP_SLEEP) @@ -556,7 +556,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#ifdef CONFIG_PPC_T1040 +#ifdef CONFIG_ARCH_T1040 #define CONFIG_PCIE4 /* PCIE controller 4 */ #endif #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ @@ -858,7 +858,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BAUDRATE 115200 #define __USB_PHY_TYPE utmi -#ifdef CONFIG_PPC_T1024 +#ifdef CONFIG_ARCH_T1024 #define CONFIG_BOARDNAME t1024rdb #define BANK_INTLV cs0_cs1 #else diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 7731809..ed568f3 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -10,8 +10,6 @@ /* * T104x RDB board configuration file */ -#define CONFIG_T104xRDB - #define CONFIG_E500 /* BOOKE e500 family */ #include <asm/config_mpc85xx.h> @@ -56,23 +54,23 @@ #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -#ifdef CONFIG_T1040RDB +#ifdef CONFIG_TARGET_T1040RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg #endif -#ifdef CONFIG_T1042RDB_PI +#ifdef CONFIG_TARGET_T1042RDB_PI #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg #endif -#ifdef CONFIG_T1042RDB +#ifdef CONFIG_TARGET_T1042RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg #endif -#ifdef CONFIG_T1040D4RDB +#ifdef CONFIG_TARGET_T1040D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg #endif -#ifdef CONFIG_T1042D4RDB +#ifdef CONFIG_TARGET_T1042D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg #endif @@ -90,23 +88,23 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#ifdef CONFIG_T1040RDB +#ifdef CONFIG_TARGET_T1040RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg #endif -#ifdef CONFIG_T1042RDB_PI +#ifdef CONFIG_TARGET_T1042RDB_PI #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg #endif -#ifdef CONFIG_T1042RDB +#ifdef CONFIG_TARGET_T1042RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg #endif -#ifdef CONFIG_T1040D4RDB +#ifdef CONFIG_TARGET_T1040D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg #endif -#ifdef CONFIG_T1042D4RDB +#ifdef CONFIG_TARGET_T1042D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg #endif @@ -124,23 +122,23 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#ifdef CONFIG_T1040RDB +#ifdef CONFIG_TARGET_T1040RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg #endif -#ifdef CONFIG_T1042RDB_PI +#ifdef CONFIG_TARGET_T1042RDB_PI #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg #endif -#ifdef CONFIG_T1042RDB +#ifdef CONFIG_TARGET_T1042RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg #endif -#ifdef CONFIG_T1040D4RDB +#ifdef CONFIG_TARGET_T1040D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg #endif -#ifdef CONFIG_T1042D4RDB +#ifdef CONFIG_TARGET_T1042D4RDB #define CONFIG_SYS_FSL_PBL_RCW \ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif @@ -342,13 +340,13 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 -#if defined(CONFIG_T1042RDB_PI) +#if defined(CONFIG_TARGET_T1042RDB_PI) #define CPLD_DIU_SEL_DFP 0x80 -#elif defined(CONFIG_T1042D4RDB) +#elif defined(CONFIG_TARGET_T1042D4RDB) #define CPLD_DIU_SEL_DFP 0xc0 #endif -#if defined(CONFIG_T1040D4RDB) +#if defined(CONFIG_TARGET_T1040D4RDB) #define CPLD_INT_MASK_ALL 0xFF #define CPLD_INT_MASK_THERM 0x80 #define CPLD_INT_MASK_DVI_DFP 0x40 @@ -516,7 +514,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) -#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) +#if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) /* Video */ #define CONFIG_FSL_DIU_FB @@ -547,11 +545,11 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 -#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #define I2C_MUX_CH_DEFAULT 0x8 -#endif -#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) +#if defined(CONFIG_TARGET_T1042RDB_PI) || \ + defined(CONFIG_TARGET_T1040D4RDB) || \ + defined(CONFIG_TARGET_T1042D4RDB) /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 @@ -706,10 +704,8 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME -#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #define CONFIG_QE #define CONFIG_U_QE -#endif /* Default address of microcode for the Linux Fman driver */ #if defined(CONFIG_SPIFLASH) @@ -735,7 +731,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif -#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_QE_FW_ADDR 0x130000 #elif defined(CONFIG_SDCARD) @@ -745,7 +740,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #else #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 #endif -#endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) @@ -758,17 +752,17 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif #ifdef CONFIG_FMAN_ENET -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 -#elif defined(CONFIG_T1040D4RDB) +#elif defined(CONFIG_TARGET_T1040D4RDB) #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 -#elif defined(CONFIG_T1042D4RDB) +#elif defined(CONFIG_TARGET_T1042D4RDB) #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 #endif -#ifdef CONFIG_T104XD4RDB +#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 #else @@ -777,10 +771,10 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif /* Enable VSC9953 L2 Switch driver on T1040 SoC */ -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) +#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) #define CONFIG_VSC9953 #define CONFIG_CMD_ETHSW -#ifdef CONFIG_T1040RDB +#ifdef CONFIG_TARGET_T1040RDB #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 #else @@ -803,7 +797,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* * Command line configuration. */ -#ifdef CONFIG_T1042RDB_PI +#ifdef CONFIG_TARGET_T1042RDB_PI #define CONFIG_CMD_DATE #endif #define CONFIG_CMD_ERRATA @@ -881,15 +875,15 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define __USB_PHY_TYPE utmi #define RAMDISKFILE "t104xrdb/ramdisk.uboot" -#ifdef CONFIG_T1040RDB +#ifdef CONFIG_TARGET_T1040RDB #define FDTFILE "t1040rdb/t1040rdb.dtb" -#elif defined(CONFIG_T1042RDB_PI) +#elif defined(CONFIG_TARGET_T1042RDB_PI) #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" -#elif defined(CONFIG_T1042RDB) +#elif defined(CONFIG_TARGET_T1042RDB) #define FDTFILE "t1042rdb/t1042rdb.dtb" -#elif defined(CONFIG_T1040D4RDB) +#elif defined(CONFIG_TARGET_T1040D4RDB) #define FDTFILE "t1042rdb/t1040d4rdb.dtb" -#elif defined(CONFIG_T1042D4RDB) +#elif defined(CONFIG_TARGET_T1042D4RDB) #define FDTFILE "t1042rdb/t1042d4rdb.dtb" #endif diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 8702a45..17176f4 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -14,13 +14,13 @@ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #define CONFIG_MMC #define CONFIG_USB_EHCI -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) #define CONFIG_T2080QDS #define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ -#elif defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2081) #define CONFIG_T2081QDS #endif @@ -69,9 +69,9 @@ #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg -#elif defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2081) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg #endif #define CONFIG_SPL_NAND_BOOT @@ -88,9 +88,9 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg -#elif defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2081) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg #endif #define CONFIG_SPL_SPI_BOOT @@ -107,9 +107,9 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#if defined(CONFIG_PPC_T2080) +#if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg -#elif defined(CONFIG_PPC_T2081) +#elif defined(CONFIG_ARCH_T2081) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg #endif #define CONFIG_SPL_MMC_BOOT diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 6ba2a03..1d18316 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_T4240QDS - #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ @@ -544,7 +542,7 @@ unsigned long get_board_ddr_clk(void); * interleaving. It can be cacheline, page, bank, superbank. * See doc/README.fsl-ddr for details. */ -#ifdef CONFIG_PPC_T4240 +#ifdef CONFIG_ARCH_T4240 #define CTRL_INTLV_PREFERED 3way_4KB #else #define CTRL_INTLV_PREFERED cacheline diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 2fac19f..6c743e3 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_T4240RDB - #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 @@ -734,7 +732,7 @@ unsigned long get_board_ddr_clk(void); * interleaving. It can be cacheline, page, bank, superbank. * See doc/README.fsl-ddr for details. */ -#ifdef CONFIG_PPC_T4240 +#ifdef CONFIG_ARCH_T4240 #define CTRL_INTLV_PREFERED 3way_4KB #else #define CTRL_INTLV_PREFERED cacheline diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index ce1cf97..1163b0d 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -27,7 +27,6 @@ #define CONFIG_UCP1020_REV_1_3 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" -#define CONFIG_P1020 #define CONFIG_TSEC_ENET #define CONFIG_TSEC1 @@ -59,7 +58,6 @@ #define CONFIG_UCP1020_REV_1_3 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" -#define CONFIG_P1020 #define CONFIG_TSEC_ENET #define CONFIG_TSEC1 diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 5e1f1b0..b824e3b 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -37,7 +37,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_P1022 #define CONFIG_CONTROLCENTERD #define CONFIG_MP /* support multiple processors */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 3807d45..67a5034 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -24,13 +24,13 @@ #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg -#if defined(CONFIG_P3041DS) +#if defined(CONFIG_TARGET_P3041DS) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg -#elif defined(CONFIG_P4080DS) +#elif defined(CONFIG_TARGET_P4080DS) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg -#elif defined(CONFIG_P5020DS) +#elif defined(CONFIG_TARGET_P5020DS) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg -#elif defined(CONFIG_P5040DS) +#elif defined(CONFIG_TARGET_P5040DS) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg #endif #endif @@ -680,7 +680,7 @@ #define CONFIG_BAUDRATE 115200 -#ifdef CONFIG_P4080DS +#ifdef CONFIG_TARGET_P4080DS #define __USB_PHY_TYPE ulpi #else #define __USB_PHY_TYPE utmi diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 4a11092..13e4690 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -9,7 +9,7 @@ #define CONFIG_CYRUS -#if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040) +#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) #error Must call Cyrus CONFIG with a specific CPU enabled. #endif @@ -18,7 +18,7 @@ #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE3 #define CONFIG_PCIE4 -#ifdef CONFIG_PPC_P5020 +#ifdef CONFIG_ARCH_P5020 #define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_SYS_DPAA_RMAN #endif @@ -30,10 +30,10 @@ #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg -#if defined(CONFIG_PPC_P5020) +#if defined(CONFIG_ARCH_P5020) #define CONFIG_SYS_CLK_FREQ 133000000 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg -#elif defined(CONFIG_PPC_P5040) +#elif defined(CONFIG_ARCH_P5040) #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg #endif diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index f557ee2..fad8865 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -8,8 +8,6 @@ #ifndef _CONFIG_KMP204X_H #define _CONFIG_KMP204X_H -#define CONFIG_PPC_P2041 - #define CONFIG_SYS_TEXT_BASE 0xfff40000 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 523af52..77f3d81 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -10,9 +10,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#if defined(CONFIG_P1020MBG) +#if defined(CONFIG_TARGET_P1020MBG) #define CONFIG_BOARDNAME "P1020MBG-PC" -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -21,19 +20,17 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1020UTM) +#if defined(CONFIG_TARGET_P1020UTM) #define CONFIG_BOARDNAME "P1020UTM-PC" -#define CONFIG_P1020 #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xe0 #define __SW_BOOT_SD 0x50 #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1020RDB_PC) +#if defined(CONFIG_TARGET_P1020RDB_PC) #define CONFIG_BOARDNAME "P1020RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -58,10 +55,9 @@ * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off */ -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_BOARDNAME "P1020RDB-PD" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -83,10 +79,9 @@ "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" #endif -#if defined(CONFIG_P1021RDB) +#if defined(CONFIG_TARGET_P1021RDB) #define CONFIG_BOARDNAME "P1021RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1021 #define CONFIG_QE #define CONFIG_VSC7385_ENET #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of @@ -118,10 +113,9 @@ #endif #endif -#if defined(CONFIG_P1024RDB) +#if defined(CONFIG_TARGET_P1024RDB) #define CONFIG_BOARDNAME "P1024RDB" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1024 #define CONFIG_SLIC #define __SW_BOOT_MASK 0xf3 #define __SW_BOOT_NOR 0x00 @@ -131,10 +125,9 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1025RDB) +#if defined(CONFIG_TARGET_P1025RDB) #define CONFIG_BOARDNAME "P1025RDB" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1025 #define CONFIG_QE #define CONFIG_SLIC @@ -148,10 +141,9 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P2020RDB) -#define CONFIG_BOARDNAME "P2020RDB-PCA" +#if defined(CONFIG_TARGET_P2020RDB) +#define CONFIG_BOARDNAME "P2020RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P2020 #define CONFIG_VSC7385_ENET #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xc8 @@ -292,7 +284,7 @@ #define CONFIG_LIBATA #define CONFIG_LBA48 -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_TARGET_P2020RDB) #define CONFIG_SYS_CLK_FREQ 100000000 #else #define CONFIG_SYS_CLK_FREQ 66666666 @@ -336,7 +328,7 @@ #define SPD_EEPROM_ADDRESS 0x52 #undef CONFIG_FSL_DDR_INTERACTIVE -#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) +#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G #define CONFIG_CHIP_SELECTS_PER_CTRL 2 #else @@ -351,7 +343,7 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Default settings for DDR3 */ -#ifndef CONFIG_P2020RDB +#ifndef CONFIG_TARGET_P2020RDB #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 @@ -406,10 +398,10 @@ /* * Local Bus Definitions */ -#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) +#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ #define CONFIG_SYS_FLASH_BASE 0xec000000 -#elif defined(CONFIG_P1020UTM) +#elif defined(CONFIG_TARGET_P1020UTM) #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ #define CONFIG_SYS_FLASH_BASE 0xee000000 #else @@ -455,7 +447,7 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #else #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) @@ -466,7 +458,7 @@ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ | OR_FCM_PGS /* Large Page*/ \ | OR_FCM_CSCT \ @@ -584,7 +576,7 @@ #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_TARGET_P2020RDB) #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) #else #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) @@ -755,7 +747,7 @@ #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #endif /* CONFIG_QE */ -#ifdef CONFIG_P1025RDB +#ifdef CONFIG_TARGET_P1025RDB /* * QE UEC ethernet configuration */ @@ -789,7 +781,7 @@ #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 #endif /* CONFIG_UEC_ETH5 */ -#endif /* CONFIG_P1025RDB */ +#endif /* CONFIG_TARGET_P1025RDB */ /* * Environment @@ -853,7 +845,7 @@ #endif #endif -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index ef32181..c122f8e 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -12,7 +12,6 @@ #if defined(CONFIG_TWR_P1025) #define CONFIG_BOARDNAME "TWR-P1025" -#define CONFIG_P1025 #define CONFIG_PHY_ATHEROS #define CONFIG_QE #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index a7f2a9d..2c85f65 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -15,7 +15,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_QEMU_E500 #undef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index e9f9d30..008781e 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -38,7 +38,6 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_SBC8548 1 /* SBC8548 board specific */ /* diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 361c96c..2bd89f4 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -21,7 +21,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ #define CONFIG_MP 1 /* support multiple processors */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 753ccfb..c697f63 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -20,7 +20,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8544 1 #define CONFIG_SOCRATES 1 #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 027440a..6d95789 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -14,7 +14,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ #define CONFIG_SYS_BOARD_NAME "XPedite5170" #define CONFIG_SYS_FORM_3U_VPX 1 diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index d980c15..7f6927b 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -16,7 +16,6 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8548 1 #define CONFIG_XPEDITE5200 1 #define CONFIG_SYS_BOARD_NAME "XPedite5200" #define CONFIG_SYS_FORM_PMC_XMC 1 diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index a82eef5..a6bdffc 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -16,8 +16,6 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8572 1 -#define CONFIG_XPEDITE5370 1 #define CONFIG_SYS_BOARD_NAME "XPedite5370" #define CONFIG_SYS_FORM_3U_VPX 1 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 973089b..f12f8fe 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -16,7 +16,6 @@ */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_P2020 1 #define CONFIG_XPEDITE550X 1 #define CONFIG_SYS_BOARD_NAME "XPedite5500" #define CONFIG_SYS_FORM_PMC_XMC 1 |