Merge git://git.denx.de/u-boot-socfpga

Conflicts:
	include/configs/axs101.h

Signed-off-by: Tom Rini <trini@konsulko.com>

16 files changed, 92 insertions, 40 deletions

diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index c92cca2..98fff63 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -95,16 +95,10 @@
 /*
  * Ethernet PHY configuration
  */
-#define CONFIG_PHYLIB
 #define CONFIG_MII
 #define CONFIG_PHY_GIGE
 
 /*
- * Ethernet configuration
- */
-#define CONFIG_DW_AUTONEG
-
-/*
  * USB 1.1 configuration
  */
 #define CONFIG_USB_OHCI_NEW
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index 0e353b9..b5d4847 100644
--- a/include/configs/bf609-ezkit.h
+++ b/include/configs/bf609-ezkit.h
@@ -75,7 +75,6 @@
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_CMD_MII
 #define CONFIG_MII
-#define CONFIG_PHYLIB
 
 /* i2c Settings */
 #define CONFIG_SYS_I2C
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index eb16a5e..14a42b1 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -45,7 +45,6 @@
 /* 10/100M Ethernet support */
 #define CONFIG_DESIGNWARE_ETH
 #define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_PHYLIB
 
 /* Environment configuration */
 #define CONFIG_ENV_SECT_SIZE		0x1000
diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h
index 3d5665d..a0161bc 100644
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -52,8 +52,6 @@
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
-#define CONFIG_ENV_OFFSET		512	/* just after the MBR */
 
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -72,11 +70,13 @@
 	"mmcload=mmc rescan;" \
 		"load mmc 0:1 ${loadaddr} ${bootimage};" \
 		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-	"qspiroot=/dev/mtdblock0\0" \
-	"qspirootfstype=jffs2\0" \
+	"qspiload=sf probe && mtdparts default && run ubiload\0" \
 	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
-		"bootm ${loadaddr} - ${fdt_addr}\0"
+		" ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"ubiload=ubi part UBI && ubifsmount ubi0 && " \
+		"ubifsload ${loadaddr} /boot/${bootimage} && " \
+		"ubifsload ${fdt_addr} /boot/${fdtimage}\0"
 
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 3a4df63..a09e906 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -109,7 +109,6 @@
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_MII
 #define CONFIG_AUTONEG_TIMEOUT		(15 * CONFIG_SYS_HZ)
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_GIGE
 #endif
 
@@ -162,6 +161,19 @@
 #endif
 
 /*
+ * NAND Support
+ */
+#ifdef CONFIG_NAND_DENALI
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_DENALI_ECC_SIZE	512
+#define CONFIG_SYS_NAND_REGS_BASE	SOCFPGA_NANDREGS_ADDRESS
+#define CONFIG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_DATA_BASE + 0x10)
+#endif
+
+/*
  * I2C support
  */
 #define CONFIG_SYS_I2C
@@ -197,7 +209,7 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
-#define MTDIDS_DEFAULT			"nor0=ff705000.spi"
+#define MTDIDS_DEFAULT			"nor0=ff705000.spi.0"
 #endif
 /* QSPI reference clock */
 #ifndef __ASSEMBLY__
@@ -249,7 +261,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
 #define CONFIG_USB_FUNCTION_DFU
+#ifdef CONFIG_DM_MMC
 #define CONFIG_DFU_MMC
+#endif
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(32 * 1024 * 1024)
 #define DFU_DEFAULT_POLL_TIMEOUT	300
 
@@ -271,6 +285,43 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 #define CONFIG_ENV_SIZE			4096
 
+/* Environment for SDMMC boot */
+#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
+#define CONFIG_ENV_OFFSET		512	/* just after the MBR */
+#endif
+
+/*
+ * mtd partitioning for serial NOR flash
+ *
+ * device nor0 <ff705000.spi.0>, # parts = 6
+ * #: name                size            offset          mask_flags
+ * 0: u-boot              0x00100000      0x00000000      0
+ * 1: env1                0x00040000      0x00100000      0
+ * 2: env2                0x00040000      0x00140000      0
+ * 3: UBI                 0x03e80000      0x00180000      0
+ * 4: boot                0x00e80000      0x00180000      0
+ * 5: rootfs              0x01000000      0x01000000      0
+ *
+ */
+#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
+#define MTDPARTS_DEFAULT	"mtdparts=ff705000.spi.0:"\
+				"1m(u-boot),"		\
+				"256k(env1),"		\
+				"256k(env2),"		\
+				"14848k(boot),"		\
+				"16m(rootfs),"		\
+				"-@1536k(UBI)\0"
+#endif
+
+/* UBI and UBIFS support */
+#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#endif
+
 /*
  * SPL
  *
@@ -294,8 +345,15 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_WATCHDOG_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
+#ifdef CONFIG_DM_MMC
 #define CONFIG_SPL_MMC_SUPPORT
+#endif
+#ifdef CONFIG_DM_SPI
 #define CONFIG_SPL_SPI_SUPPORT
+#endif
+#ifdef CONFIG_SPL_NAND_DENALI
+#define CONFIG_SPL_NAND_SUPPORT
+#endif
 
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT
@@ -318,6 +376,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x40000
 #endif
 
+/* SPL NAND boot support */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#endif
+
 /*
  * Stack setup
  */
diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
index d2efdda..c4c4ecb 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -52,8 +52,6 @@
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
-#define CONFIG_ENV_OFFSET		512	/* just after the MBR */
 
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -72,11 +70,13 @@
 	"mmcload=mmc rescan;" \
 		"load mmc 0:1 ${loadaddr} ${bootimage};" \
 		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-	"qspiroot=/dev/mtdblock0\0" \
-	"qspirootfstype=jffs2\0" \
+	"qspiload=sf probe && mtdparts default && run ubiload\0" \
 	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
-		"bootm ${loadaddr} - ${fdt_addr}\0"
+		" ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"ubiload=ubi part UBI && ubifsmount ubi0 && " \
+		"ubifsload ${loadaddr} /boot/${bootimage} && " \
+		"ubifsload ${fdt_addr} /boot/${fdtimage}\0"
 
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h
index 959e3af..cbc7396 100644
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -48,8 +48,6 @@
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
-#define CONFIG_ENV_OFFSET		512	/* just after the MBR */
 
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h
index cd63faf..e7b5675 100644
--- a/include/configs/socfpga_mcvevk.h
+++ b/include/configs/socfpga_mcvevk.h
@@ -45,8 +45,6 @@
 /* Environment is in MMC */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
-#define CONFIG_ENV_OFFSET		512	/* just after the MBR */
 
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS					\
diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
index 6cbe367..95e7ba6 100644
--- a/include/configs/socfpga_sockit.h
+++ b/include/configs/socfpga_sockit.h
@@ -48,8 +48,6 @@
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
-#define CONFIG_ENV_OFFSET		512	/* just after the MBR */
 
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -68,6 +66,13 @@
 	"mmcload=mmc rescan;" \
 		"load mmc 0:1 ${loadaddr} ${bootimage};" \
 		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+	"qspiload=sf probe && mtdparts default && run ubiload\0" \
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"ubiload=ubi part UBI && ubifsmount ubi0 && " \
+		"ubifsload ${loadaddr} /boot/${bootimage} && " \
+		"ubifsload ${fdt_addr} /boot/${fdtimage}\0"
 
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h
index 1d88f4f..c32a40a 100644
--- a/include/configs/socfpga_socrates.h
+++ b/include/configs/socfpga_socrates.h
@@ -48,8 +48,6 @@
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
-#define CONFIG_ENV_OFFSET		512	/* just after the MBR */
 
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index 5bd2956..fdf67ca 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -70,11 +70,13 @@
 	"mmcload=mmc rescan;" \
 		"load mmc 0:1 ${loadaddr} ${bootimage};" \
 		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-	"qspiroot=/dev/mtdblock0\0" \
-	"qspirootfstype=jffs2\0" \
+	"qspiload=sf probe && mtdparts default && run ubiload\0" \
 	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
-		"bootm ${loadaddr} - ${fdt_addr}\0"
+		" ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"ubiload=ubi part UBI && ubifsmount ubi0 && " \
+		"ubifsload ${loadaddr} /boot/${bootimage} && " \
+		"ubifsload ${fdt_addr} /boot/${fdtimage}\0"
 
 /* Environment */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 1d69477..d2630f4 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -17,7 +17,6 @@
 
 /* Ethernet driver configuration */
 #define CONFIG_MII
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
 #define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */
 
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index 14c6a9e..f421321 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -53,7 +53,6 @@
 /* GMAC related configs */
 
 #define CONFIG_MII
-#define CONFIG_PHYLIB
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_PHY_MICREL
 
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 8042073..790e704 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -309,11 +309,9 @@ extern int soft_i2c_gpio_scl;
 #endif
 
 #ifdef CONFIG_SUNXI_GMAC
-#define CONFIG_DW_AUTONEG
 #define CONFIG_PHY_GIGE			/* GMAC can use gigabit PHY	*/
 #define CONFIG_PHY_ADDR		1
 #define CONFIG_MII			/* MII PHY management		*/
-#define CONFIG_PHYLIB
 #endif
 
 #ifdef CONFIG_USB_EHCI_HCD
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index 8660ed4..e06484f 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -42,7 +42,6 @@
 /*
  * Ethernet PHY configuration
  */
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_GIGE
 
 /*
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 58f1aca..0263c50 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -77,7 +77,6 @@
 
 /* Ethernet config options */
 #define CONFIG_MII
-#define CONFIG_PHYLIB
 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
 #define CONFIG_PHY_ADDR		0	/* PHY address */
 #define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */