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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-05-30 14:45:06 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-05-30 14:45:06 +0200
commita19b0dd62d7b8efc658fa1aa685ff5665878f3ee (patch)
tree1fadf0fb3da83203ba28f209ec99e1b33e03f4d5 /include/configs
parent60985bba58e7695dac1fddae8cdbb62d8cfd1254 (diff)
parenta71d45d706a5b51c348160163b6c159632273fed (diff)
downloadu-boot-imx-a19b0dd62d7b8efc658fa1aa685ff5665878f3ee.zip
u-boot-imx-a19b0dd62d7b8efc658fa1aa685ff5665878f3ee.tar.gz
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Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
Diffstat (limited to 'include/configs')
-rw-r--r--include/configs/Alaska8220.h334
-rw-r--r--include/configs/B4860QDS.h16
-rw-r--r--include/configs/T4240QDS.h1
-rw-r--r--include/configs/Yukon8220.h326
-rw-r--r--include/configs/bf527-ezkit.h12
-rw-r--r--include/configs/bf537-stamp.h10
-rw-r--r--include/configs/bf548-ezkit.h25
-rw-r--r--include/configs/bf561-ezkit.h5
-rw-r--r--include/configs/bf609-ezkit.h10
-rw-r--r--include/configs/bfin_adi_common.h14
-rw-r--r--include/configs/coreboot.h18
-rw-r--r--include/configs/corenet_ds.h2
-rw-r--r--include/configs/microblaze-generic.h3
-rw-r--r--include/configs/sorcery.h298
-rw-r--r--include/configs/t4qds.h45
15 files changed, 113 insertions, 1006 deletions
diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h
deleted file mode 100644
index 39c29ec..0000000
--- a/include/configs/Alaska8220.h
+++ /dev/null
@@ -1,334 +0,0 @@
-/*
- * (C) Copyright 2004
- * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC8220 1
-#define CONFIG_ALASKA8220 1 /* ... on Alaska board */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
- determine the CPU speed. */
-#define CONFIG_SYS_MPC8220_CLKIN 30000000/* ... running at 30MHz */
-#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
-
-/*
- * Serial console configuration
- */
-
-/* Define this for PSC console
-#define CONFIG_PSC_CONSOLE 1
-*/
-
-#define CONFIG_EXTUART_CONSOLE 1
-
-#ifdef CONFIG_EXTUART_CONSOLE
-# define CONFIG_CONS_INDEX 1
-# define CONFIG_SYS_NS16550_SERIAL
-# define CONFIG_SYS_NS16550
-# define CONFIG_SYS_NS16550_REG_SIZE 1
-# define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CPLD_BASE + 0x1008)
-# define CONFIG_SYS_NS16550_CLK 18432000
-#endif
-
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_MII
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTARGS "root=/dev/ram rw"
-#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
-#define CONFIG_IPADDR 192.162.1.2
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SERVERIP 192.162.1.1
-#define CONFIG_GATEWAYIP 192.162.1.1
-#define CONFIG_HOSTNAME Alaska
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_MODULE 1
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
-/*
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0
-#define CONFIG_ENV_SIZE 256
-*/
-
-/* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
- else undefined it will boot from Intel Strata flash */
-#define CONFIG_SYS_AMD_BOOT 1
-
-/*
- * Flexbus Chipselect configuration
- */
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_SYS_CS0_BASE 0xfff0
-#define CONFIG_SYS_CS0_MASK 0x00080000 /* 512 KB */
-#define CONFIG_SYS_CS0_CTRL 0x003f0d40
-
-#define CONFIG_SYS_CS1_BASE 0xfe00
-#define CONFIG_SYS_CS1_MASK 0x01000000 /* 16 MB */
-#define CONFIG_SYS_CS1_CTRL 0x003f1540
-#else
-#define CONFIG_SYS_CS0_BASE 0xff00
-#define CONFIG_SYS_CS0_MASK 0x01000000 /* 16 MB */
-#define CONFIG_SYS_CS0_CTRL 0x003f1540
-
-#define CONFIG_SYS_CS1_BASE 0xfe08
-#define CONFIG_SYS_CS1_MASK 0x00080000 /* 512 KB */
-#define CONFIG_SYS_CS1_CTRL 0x003f0d40
-#endif
-
-#define CONFIG_SYS_CS2_BASE 0xf100
-#define CONFIG_SYS_CS2_MASK 0x00040000
-#define CONFIG_SYS_CS2_CTRL 0x003f1140
-
-#define CONFIG_SYS_CS3_BASE 0xf200
-#define CONFIG_SYS_CS3_MASK 0x00040000
-#define CONFIG_SYS_CS3_CTRL 0x003f1100
-
-
-#define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
-#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_CS1_BASE << 16)
-
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH1_BASE + 0xf00000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_AMD_BASE
-#else
-#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH0_BASE + 0xf00000
-#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH1_BASE
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_INTEL_BASE
-#endif
-
-#define CONFIG_SYS_CPLD_BASE (CONFIG_SYS_CS2_BASE << 16)
-#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_CS3_BASE << 16)
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-
-#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
-#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
-
-#define CONFIG_SYS_FLASH_CHECKSUM
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
-#define CONFIG_ENV_SIZE PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
-#define CONFIG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
-#define CONFIG_ENV_SIZE PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
-#define CONFIG_ENV1_SIZE PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
-#endif
-
-#define CONFIG_ENV_OVERWRITE 1
-
-#if defined CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-#define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_SRAM_SIZE 0x8000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/* SDRAM configuration */
-#define CONFIG_SYS_SDRAM_TOTAL_BANKS 2
-#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
-#define CONFIG_SYS_SDRAM_SPD_SIZE 0x40
-#define CONFIG_SYS_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
-
-/* SDRAM drive strength register */
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
- (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
- (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
- (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
- (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC8220_FEC 1
-#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
-#define CONFIG_PHY_ADDR 0x18
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-/*
- * JFFS2 partitions
- */
-
-/* No command line, one static partition */
-/*
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0x00400000
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-*/
-
-/* mtdparts command line support */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=alaska-0"
-#define MTDPARTS_DEFAULT "mtdparts=alaska-0:4m(user)"
-*/
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index b09119a..1c9d08e 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -36,7 +36,6 @@
/* High Level Configuration Options */
#define CONFIG_BOOKE
-#define CONFIG_E6500
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
@@ -528,6 +527,15 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SF_DEFAULT_MODE 0
/*
+ * MAPLE
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
+#else
+#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
+#endif
+
+/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
@@ -623,7 +631,11 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
+
+/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
+#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
+
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 76b3ca6..6dd5c0d 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -25,7 +25,6 @@
*/
#define CONFIG_T4240QDS
#define CONFIG_PHYS_64BIT
-#define CONFIG_PPC_T4240
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE4
diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h
deleted file mode 100644
index 5f925b3..0000000
--- a/include/configs/Yukon8220.h
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * (C) Copyright 2004
- * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC8220 1
-#define CONFIG_YUKON8220 1 /* ... on Yukon board */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
- determine the CPU speed. */
-#define CONFIG_SYS_MPC8220_CLKIN 30000000/* ... running at 30MHz */
-#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
-
-/*
- * Serial console configuration
- */
-
-/* Define this for PSC console
-#define CONFIG_PSC_CONSOLE 1
-*/
-
-#define CONFIG_EXTUART_CONSOLE 1
-
-#ifdef CONFIG_EXTUART_CONSOLE
-# define CONFIG_CONS_INDEX 1
-# define CONFIG_SYS_NS16550_SERIAL
-# define CONFIG_SYS_NS16550
-# define CONFIG_SYS_NS16550_REG_SIZE 1
-# define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CPLD_BASE + 0x1008)
-# define CONFIG_SYS_NS16550_CLK 18432000
-#endif
-
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_MII
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTARGS "root=/dev/ram rw"
-#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
-#define CONFIG_IPADDR 192.162.1.2
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SERVERIP 192.162.1.1
-#define CONFIG_GATEWAYIP 192.162.1.1
-#define CONFIG_HOSTNAME yukon
-#define CONFIG_OVERWRITE_ETHADDR_ONCE
-
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_MODULE 1
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
-/*
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_OFFSET 0
-#define CONFIG_ENV_SIZE 256
-*/
-
-/* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
- else undefined it will boot from Intel Strata flash */
-#define CONFIG_SYS_AMD_BOOT 1
-
-/*
- * Flexbus Chipselect configuration
- */
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_SYS_CS0_BASE 0xfff0
-#define CONFIG_SYS_CS0_MASK 0x00080000 /* 512 KB */
-#define CONFIG_SYS_CS0_CTRL 0x003f0d40
-
-#define CONFIG_SYS_CS1_BASE 0xfe00
-#define CONFIG_SYS_CS1_MASK 0x01000000 /* 16 MB */
-#define CONFIG_SYS_CS1_CTRL 0x003f1540
-#else
-#define CONFIG_SYS_CS0_BASE 0xff00
-#define CONFIG_SYS_CS0_MASK 0x01000000 /* 16 MB */
-#define CONFIG_SYS_CS0_CTRL 0x003f1540
-
-#define CONFIG_SYS_CS1_BASE 0xfe08
-#define CONFIG_SYS_CS1_MASK 0x00080000 /* 512 KB */
-#define CONFIG_SYS_CS1_CTRL 0x003f0d40
-#endif
-
-#define CONFIG_SYS_CS2_BASE 0xf100
-#define CONFIG_SYS_CS2_MASK 0x00040000
-#define CONFIG_SYS_CS2_CTRL 0x003f1140
-
-#define CONFIG_SYS_CS3_BASE 0xf200
-#define CONFIG_SYS_CS3_MASK 0x00040000
-#define CONFIG_SYS_CS3_CTRL 0x003f1100
-
-
-#define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
-#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_CS1_BASE << 16)
-
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH1_BASE + 0xf00000
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_AMD_BASE
-#else
-#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH0_BASE + 0xf00000
-#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH1_BASE
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_INTEL_BASE
-#endif
-
-#define CONFIG_SYS_CPLD_BASE (CONFIG_SYS_CS2_BASE << 16)
-#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_CS3_BASE << 16)
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-
-#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
-#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
-
-#define CONFIG_SYS_FLASH_CHECKSUM
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#if defined (CONFIG_SYS_AMD_BOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
-#define CONFIG_ENV_SIZE PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
-#define CONFIG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
-#define CONFIG_ENV_SIZE PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
-#define CONFIG_ENV1_SIZE PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
-#endif
-
-#define CONFIG_ENV_OVERWRITE 1
-
-#if defined CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-#ifndef CONFIG_SYS_JFFS2_FIRST_SECTOR
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
-#endif
-#ifndef CONFIG_SYS_JFFS2_FIRST_BANK
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#endif
-#ifndef CONFIG_SYS_JFFS2_NUM_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-#endif
-#define CONFIG_SYS_JFFS2_LAST_BANK (CONFIG_SYS_JFFS2_FIRST_BANK + CONFIG_SYS_JFFS2_NUM_BANKS - 1)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-#define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_SRAM_SIZE 0x8000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/* SDRAM configuration */
-#define CONFIG_SYS_SDRAM_TOTAL_BANKS 2
-#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
-#define CONFIG_SYS_SDRAM_SPD_SIZE 0x40
-#define CONFIG_SYS_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
-
-/* SDRAM drive strength register */
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
- (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
- (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
- (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
- (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC8220_FEC 1
-#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
-#define CONFIG_PHY_ADDR 0x18
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index 7b51b53..db1b613 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -149,10 +149,15 @@
#define CONFIG_MUSB_TIMEOUT 100000
#endif
+/* Don't waste time transferring a logo over the UART */
+#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
+/*# define CONFIG_VIDEO*/
+#endif
/*
* Video Settings
*/
+#ifdef CONFIG_VIDEO
#ifdef CONFIG_BF527_EZKIT_REV_2_1
# define CONFIG_LQ035Q1_SPI_BUS 0
# define CONFIG_LQ035Q1_SPI_CS 7
@@ -166,7 +171,7 @@
#else
# define EASYLOGO_HEADER <asm/bfin_logo_230x230_lzma.h>
#endif
-
+#endif /* CONFIG_VIDEO */
/*
* Misc Settings
@@ -175,11 +180,6 @@
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
-/* Don't waste time transferring a logo over the UART */
-#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
-# define CONFIG_VIDEO
-#endif
-
/*
* Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 05029d4..25cebf8 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -52,7 +52,7 @@
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
@@ -135,15 +135,17 @@
/*
* SPI_MMC Settings
*/
+#define CONFIG_MMC_SPI
+#ifdef CONFIG_MMC_SPI
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC_SPI
-
+#endif
/*
* NAND Settings
*/
/* #define CONFIG_NAND_PLAT */
+#ifdef CONFIG_NAND_PLAT
#define CONFIG_SYS_NAND_BASE 0x20212000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
@@ -158,7 +160,7 @@
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3
-
+#endif /* CONFIG_NAND_PLAT */
/*
* CF-CARD IDE-HDD Support
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index e6b05db..da5f029 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -120,18 +120,16 @@
#define CONFIG_ENV_SECT_SIZE 0x8000
#endif
-
/*
* NAND Settings
*/
-#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-# define CONFIG_BFIN_NFC_BOOTROM_ECC
-#endif
+#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
+#define CONFIG_BFIN_NFC_BOOTROM_ECC
#define CONFIG_DRIVER_NAND_BFIN
-#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
+#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#endif
/*
* I2C Settings
@@ -184,13 +182,12 @@
#define CONFIG_UART_CONSOLE 1
#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
-#ifndef __ADSPBF542__
-/* Don't waste time transferring a logo over the UART */
-# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
-# define CONFIG_VIDEO
-# define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h>
-# endif
-# define CONFIG_DEB_DMA_URGENT
+#define CONFIG_ADI_GPIO2
+
+#undef CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h >
+#define CONFIG_DEB_DMA_URGENT
#endif
/* Define if want to do post memory test */
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 1a9d27e..6ee1e4c 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -98,6 +98,11 @@
*/
#define CONFIG_UART_CONSOLE 0
+/*
+ * Run core 1 from L1 SRAM start address when init uboot on core 0
+ */
+/* #define CONFIG_CORE1_RUN 1 */
+
/*
* Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index 02149fa..1a43e1b 100644
--- a/include/configs/bf609-ezkit.h
+++ b/include/configs/bf609-ezkit.h
@@ -144,10 +144,13 @@
#define CONFIG_UART_CONSOLE 0
#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_SOFTSWITCH
#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4)
#define CONFIG_BFIN_SOFT_SWITCH
+#define CONFIG_ADI_GPIO2
+
#if 0
#define CONFIG_UART_MEM 1024
#undef CONFIG_UART_CONSOLE
@@ -155,6 +158,13 @@
#undef CONFIG_UART_CONSOLE_IS_JTAG
#endif
+#define CONFIG_BOARD_SIZE_LIMIT $$((512 * 1024))
+
+/*
+ * Run core 1 from L1 SRAM start address when init uboot on core 0
+ */
+/* #define CONFIG_CORE1_RUN 1 */
+
/*
* Pull in common ADI header for remaining command/environment setup
*/
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index d3ae3a7..e1a6fe3 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -111,8 +111,8 @@
#ifndef CONFIG_BAUDRATE
# define CONFIG_BAUDRATE 57600
#endif
-#ifndef CONFIG_DEBUG_EARLY_SERIAL
-# define CONFIG_SYS_BFIN_UART
+#ifdef CONFIG_UART_CONSOLE
+# define CONFIG_BFIN_SERIAL
#endif
/*
@@ -317,5 +317,13 @@
#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */
#define CONFIG_LZMA
#define CONFIG_MONITOR_IS_IN_RAM
-
+#ifdef CONFIG_HW_WATCHDOG
+# define CONFIG_BFIN_WATCHDOG
+# ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
+# define CONFIG_WATCHDOG_TIMEOUT_MSECS 5000
+# endif
+#endif
+#ifndef CONFIG_ADI_GPIO2
+# define CONFIG_ADI_GPIO1
+#endif
#endif
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 5bacc77..be04a75 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -38,7 +38,6 @@
#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_SYS_VSNPRINTF
-#define CONFIG_INTEL_CORE_ARCH /* Sandy bridge and ivy bridge chipsets. */
#define CONFIG_ZBOOT_32
#define CONFIG_PHYSMEM
#define CONFIG_SYS_EARLY_PCI_INIT
@@ -49,6 +48,19 @@
#define CONFIG_OF_SEPARATE
#define CONFIG_DEFAULT_DEVICE_TREE link
+#define CONFIG_BOOTSTAGE
+#define CONFIG_BOOTSTAGE_REPORT
+#define CONFIG_BOOTSTAGE_FDT
+#define CONFIG_CMD_BOOTSTAGE
+/* Place to stash bootstage data from first-stage U-Boot */
+#define CONFIG_BOOTSTAGE_STASH 0x0110f000
+#define CONFIG_BOOTSTAGE_STASH_SIZE 0x7fc
+#define CONFIG_BOOTSTAGE_USER_COUNT 60
+
+#define CONFIG_LZO
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+
/*-----------------------------------------------------------------------
* Watchdog Configuration
*/
@@ -218,7 +230,6 @@
#define CONFIG_SYS_MEMTEST_END 0x01000000
#define CONFIG_SYS_LOAD_ADDR 0x100000
#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_X86_ISR_TIMER
/*-----------------------------------------------------------------------
* SDRAM Configuration
@@ -235,8 +246,9 @@
* CPU Features
*/
-#define CONFIG_SYS_GENERIC_TIMER
+#define CONFIG_SYS_X86_TSC_TIMER
#define CONFIG_SYS_PCAT_INTERRUPTS
+#define CONFIG_SYS_PCAT_TIMER
#define CONFIG_SYS_NUM_IRQS 16
/*-----------------------------------------------------------------------
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 5cc9b5a..2e2d439 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -38,6 +38,8 @@
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
#elif defined(CONFIG_P5020DS)
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
+#elif defined(CONFIG_P5040DS)
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
#endif
#endif
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 0c4e719..17f53ba 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -104,7 +104,7 @@
/* gpio */
#ifdef XILINX_GPIO_BASEADDR
-# define CONFIG_SYS_GPIO_0 1
+# define CONFIG_XILINX_GPIO
# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
#endif
@@ -312,6 +312,7 @@
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MFSL
#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_GPIO
#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
# define CONFIG_CMD_CACHE
diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
deleted file mode 100644
index f67898e..0000000
--- a/include/configs/sorcery.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * (C) Copyright 2004
- * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC8220 1
-#define CONFIG_SORCERY 1 /* Sorcery board */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
- determine the CPU speed. */
-#define CONFIG_SYS_MPC8220_CLKIN 60000000 /* ... running at 60MHz */
-#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC */
-
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/* PCI */
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
-
-#define CONFIG_PCI_MEM_BUS 0x80000000
-#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_PCI_IO_BUS 0x71000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_PCI_CFG_BUS 0x70000000
-#define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS
-#define CONFIG_PCI_CFG_SIZE 0x01000000
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Default Environment
- */
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_HOSTNAME sorcery
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs $bootargs " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
- ":$hostname:$netdev:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
- "bootm $kernel_addr\0" \
- "flash_self=run ramargs addip;" \
- "bootm $kernel_addr $ramdisk_addr\0" \
- "net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
- "bootfile=/tftpboot/sorcery/uImage\0" \
- "kernel_addr=FFE00000\0" \
- "ramdisk_addr=FFB00000\0" \
- ""
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-#define CONFIG_EEPRO100
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_MODULE 1
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * Flexbus Chipselect configuration
- * Beware: Some CS# seem to be mandatory (if these CS# are not set,
- * board can hang-up in unpredictable place).
- * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
- */
-
-/* Flash */
-#define CONFIG_SYS_CS0_BASE 0xf800
-#define CONFIG_SYS_CS0_MASK 0x08000000 /* 128 MB (two chips) */
-#define CONFIG_SYS_CS0_CTRL 0x001019c0
-
-/* NVM */
-#define CONFIG_SYS_CS1_BASE 0xf7e8
-#define CONFIG_SYS_CS1_MASK 0x00040000 /* 256K */
-#define CONFIG_SYS_CS1_CTRL 0x00101940 /* 8bit port size */
-
-/* Atlas2 + Gemini */
-#define CONFIG_SYS_CS2_BASE 0xf7e7
-#define CONFIG_SYS_CS2_MASK 0x00010000 /* 64K*/
-#define CONFIG_SYS_CS2_CTRL 0x001011c0 /* 16bit port size */
-
-/* CAN Controller */
-#define CONFIG_SYS_CS3_BASE 0xf7e6
-#define CONFIG_SYS_CS3_MASK 0x00010000 /* 64K */
-#define CONFIG_SYS_CS3_CTRL 0x00102140 /* 8Bit port size */
-
-/* Foreign interface */
-#define CONFIG_SYS_CS4_BASE 0xf7e5
-#define CONFIG_SYS_CS4_MASK 0x00010000 /* 64K */
-#define CONFIG_SYS_CS4_CTRL 0x00101dc0 /* 16bit port size */
-
-/* CPLD */
-#define CONFIG_SYS_CS5_BASE 0xf7e4
-#define CONFIG_SYS_CS5_MASK 0x00010000 /* 64K */
-#define CONFIG_SYS_CS5_CTRL 0x001000c0 /* 16bit port size */
-
-#define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
-#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_FLASH0_BASE)
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
- CONFIG_SYS_FLASH_BASE+0x04000000 } /* two banks */
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000000 - 0x40000)
-#define CONFIG_ENV_SIZE 0x4000 /* 16K */
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + 0x20000)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-#define CONFIG_ENV_OVERWRITE 1
-
-#if defined CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_EEPROM
-#elif defined CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-#define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_SRAM_SIZE 0x8000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in DPRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/* SDRAM configuration (for SPD) */
-#define CONFIG_SYS_SDRAM_TOTAL_BANKS 1
-#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */
-#define CONFIG_SYS_SDRAM_SPD_SIZE 0x100
-#define CONFIG_SYS_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */
-
-/* SDRAM drive strength register (for SSTL_2 class II)*/
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
- (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
- (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
- (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
- (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC8220_FEC 1
-#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
-#define CONFIG_PHY_ADDR 0x1F
-#define CONFIG_MII 1
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL 0
-
-/*
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-*/
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 2c665b8..fa1dcc3 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -29,13 +29,14 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
#endif
#define CONFIG_CMD_REGINFO
/* High Level Configuration Options */
#define CONFIG_BOOKE
-#define CONFIG_E6500
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
@@ -444,11 +445,19 @@ unsigned long get_board_ddr_clk(void);
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
-/* VSC Crossbar switches */
-#define CONFIG_VSC_CROSSBAR
#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_VOL_MONITOR 0xa
#define I2C_MUX_CH_VSC3316_FS 0xc
#define I2C_MUX_CH_VSC3316_BS 0xd
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+/* VSC Crossbar switches */
+#define CONFIG_VSC_CROSSBAR
#define VSC3316_FSM_TX_ADDR 0x70
#define VSC3316_FSM_RX_ADDR 0x71
@@ -504,7 +513,7 @@ unsigned long get_board_ddr_clk(void);
*/
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_SST
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
@@ -641,15 +650,10 @@ unsigned long get_board_ddr_clk(void);
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#define XFI_CARD_PORT1_PHY_ADDR 0x1 /* tmp, FIXME below addr */
-#define XFI_CARD_PORT2_PHY_ADDR 0x2
-#define XFI_CARD_PORT3_PHY_ADDR 0x3
-#define XFI_CARD_PORT4_PHY_ADDR 0x4
-#define QSGMII_CARD_PHY_ADDR 0x5
-#define FM1_10GEC1_PHY_ADDR 0x6
-#define FM1_10GEC2_PHY_ADDR 0x7
-#define FM2_10GEC1_PHY_ADDR 0x8
-#define FM2_10GEC2_PHY_ADDR 0x9
+#define FM1_10GEC1_PHY_ADDR 0x0
+#define FM1_10GEC2_PHY_ADDR 0x1
+#define FM2_10GEC1_PHY_ADDR 0x2
+#define FM2_10GEC2_PHY_ADDR 0x3
#endif
#ifdef CONFIG_PCI
@@ -783,8 +787,21 @@ unsigned long get_board_ddr_clk(void);
#define __USB_PHY_TYPE utmi
+/*
+ * T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to
+ * cacheline interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=3way_4KB," \
+ "hwconfig=fsl_ddr:" \
+ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
"bank_intlv=auto;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \