Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts: board/davinci/da830evm/da830evm.c board/edb93xx/sdram_cfg.c board/esd/otc570/otc570.c board/netstar/eeprom.c board/netstar/eeprom_start.S cpu/arm920t/ep93xx/timer.c include/configs/netstar.h include/configs/otc570.h Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
author: Minkyu Kang <mk7.kang@samsung.com> 2010-03-15 10:51:36 +0900
committer: Minkyu Kang <mk7.kang@samsung.com> 2010-03-15 10:51:36 +0900
commit: 995a4b1d83a08223c82c1e15778b02e85e5bba51 (patch)
tree: 0acb85278216df76d8fb7284b32d6dd95a1fc978 /include/configs
parent: a8d25fc26f681a9c4dfb062ebb4b00b9509a7966 (diff)
parent: 44de3e8ff7ed48bf96ec6c5e2173187d9c1c61e6 (diff)
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48 files changed, 1538 insertions, 327 deletions
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
index 73e34bd..52ead43 100644
--- a/include/configs/AR405.h
+++ b/include/configs/AR405.h
@@ -93,6 +93,7 @@
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_MII
+#undef CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_BSP
 
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 0a4ba29..1478ec8 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -580,13 +580,6 @@
  */
 #define CONFIG_ENV_OVERWRITE
 
-#define CONFIG_ETHADDR		00:E0:0C:00:95:01
-#define CONFIG_ETH1ADDR		00:E0:0C:00:95:02
-
-#define CONFIG_IPADDR		10.0.0.2
-#define CONFIG_SERVERIP		10.0.0.1
-#define CONFIG_GATEWAYIP	10.0.0.1
-#define CONFIG_NETMASK		255.0.0.0
 #define CONFIG_NETDEV		eth1
 
 #define CONFIG_HOSTNAME		mpc8313erdb
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index cfed4ca..a8570ce 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -616,9 +616,7 @@
 
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR		04:00:00:00:00:0A
 #define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		04:00:00:00:00:0B
 #endif
 
 #define CONFIG_BAUDRATE 115200
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 356586c..4046f80 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -347,7 +347,8 @@
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	4
-#define CONFIG_SYS_UEC1_INTERFACE_MODE	ENET_100_MII
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE	MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
 #endif
 
 #define CONFIG_UEC_ETH2		/* ETH4 */
@@ -358,7 +359,8 @@
 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK3
 #define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR	0
-#define CONFIG_SYS_UEC2_INTERFACE_MODE	ENET_100_MII
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE	MII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
 #endif
 
 /*
@@ -523,17 +525,11 @@
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_HAS_ETH0				/* add support for "ethaddr" */
-#define CONFIG_ETHADDR	00:04:9f:ef:03:01
 #define CONFIG_HAS_ETH1				/* add support for "eth1addr" */
-#define CONFIG_ETH1ADDR	00:04:9f:ef:03:02
 
 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
 #define CONFIG_SYS_I2C_MAC_OFFSET	0x7f00	/* MAC address offset in I2C EEPROM */
 
-#define CONFIG_IPADDR		10.0.0.2
-#define CONFIG_SERVERIP		10.0.0.1
-#define CONFIG_GATEWAYIP	10.0.0.1
-#define CONFIG_NETMASK		255.0.0.0
 #define CONFIG_NETDEV		eth1
 
 #define CONFIG_HOSTNAME		mpc8323erdb
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index f17f9c7..2ad5f60 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -362,7 +362,8 @@
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	3
-#define CONFIG_SYS_UEC1_INTERFACE_MODE	ENET_100_MII
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE	MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
 #endif
 
 #define CONFIG_UEC_ETH2		/* ETH4 */
@@ -373,7 +374,8 @@
 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK8
 #define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR	4
-#define CONFIG_SYS_UEC2_INTERFACE_MODE	ENET_100_MII
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE	MII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
 #endif
 
 /*
@@ -542,9 +544,7 @@
 
 #if defined(CONFIG_UEC_ETH)
 #define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR	00:04:9f:ef:03:01
 #define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR	00:04:9f:ef:03:02
 #endif
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 6361c45..bf28d9e 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -685,22 +685,14 @@
 #define CONFIG_ENV_OVERWRITE
 
 #if defined(CONFIG_TSEC_ENET)
-#define CONFIG_ETHADDR		00:04:9f:ef:23:33
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH0
-#define CONFIG_ETH1ADDR		00:E0:0C:00:7E:21
 #endif
 
-#define CONFIG_IPADDR		192.168.1.253
-
 #define CONFIG_HOSTNAME		mpc8349emds
 #define CONFIG_ROOTPATH		/nfsroot/rootfs
 #define CONFIG_BOOTFILE		uImage
 
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.255.0
-
 #define CONFIG_LOADADDR		800000	/* default location for tftp and bootm */
 
 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index eaa59fd..52e2851 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -678,18 +678,6 @@ boards, we say we have two, but don't display a message if we find only one. */
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifdef CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR		00:E0:0C:00:8C:01
-#endif
-
-#ifdef CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		00:E0:0C:00:8C:02
-#endif
-
-#define CONFIG_IPADDR		192.168.1.253
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.252.0
 #define CONFIG_NETDEV		eth0
 
 #ifdef CONFIG_MPC8349ITX
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 8520155..b9b5eab 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -400,7 +400,8 @@
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK9
 #define CONFIG_SYS_UEC1_ETH_TYPE	GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	0
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 #endif
 
 #define CONFIG_UEC_ETH2		/* GETH2 */
@@ -411,7 +412,8 @@
 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK4
 #define CONFIG_SYS_UEC2_ETH_TYPE	GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR	1
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 #endif
 
 /*
@@ -585,9 +587,7 @@
 
 #if defined(CONFIG_UEC_ETH)
 #define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR	00:04:9f:ef:01:01
 #define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
 #endif
 
 #define CONFIG_BAUDRATE 115200
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 1d1f94f..c7bc9cd 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -318,7 +318,8 @@
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK9
 #define CONFIG_SYS_UEC1_ETH_TYPE	GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	2
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_RXID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 #endif
 
 #define CONFIG_UEC_ETH2		/* GETH2 */
@@ -329,7 +330,8 @@
 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK4
 #define CONFIG_SYS_UEC2_ETH_TYPE	GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR	4
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_RXID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 #endif
 
 /*
@@ -504,10 +506,6 @@
 #define CONFIG_HAS_ETH1
 #define CONFIG_HAS_ETH2
 #define CONFIG_HAS_ETH3
-#define CONFIG_ETHADDR	00:04:9f:ef:01:01
-#define CONFIG_ETH1ADDR	00:04:9f:ef:01:02
-#define CONFIG_ETH2ADDR	00:04:9f:ef:01:03
-#define CONFIG_ETH3ADDR	00:04:9f:ef:01:04
 #endif
 
 #define CONFIG_BAUDRATE 115200
@@ -516,10 +514,6 @@
 #define CONFIG_HOSTNAME	mpc8360erdk
 #define CONFIG_BOOTFILE	uImage
 
-#define CONFIG_IPADDR		10.0.0.99
-#define CONFIG_SERVERIP		10.0.0.2
-#define CONFIG_GATEWAYIP	10.0.0.2
-#define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_ROOTPATH		/nfsroot/
 
 #define	CONFIG_BOOTDELAY 2	/* -1 disables auto-boot */
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 63f1d85..65d49ec 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -637,9 +637,7 @@ extern int board_pci_host_broken(void);
 
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR		00:E0:0C:00:83:79
 #define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		00:E0:0C:00:83:78
 #endif
 
 #define CONFIG_BAUDRATE 115200
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 913184c..ca60272 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -643,20 +643,8 @@
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifdef CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR		00:04:9f:ef:04:01
-#endif
-
-#ifdef CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		00:04:9f:ef:04:02
-#endif
-
 #define CONFIG_HAS_FSL_DR_USB
 
-#define CONFIG_IPADDR		10.0.0.2
-#define CONFIG_SERVERIP		10.0.0.1
-#define CONFIG_GATEWAYIP	10.0.0.1
-#define CONFIG_NETMASK		255.0.0.0
 #define CONFIG_NETDEV		eth1
 
 #define CONFIG_HOSTNAME		mpc837x_rdb
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 128a7e1..6973538 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -333,7 +333,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16
 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR       7
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 #endif
 
 #define CONFIG_UEC_ETH2         /* GETH2 */
@@ -344,7 +345,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16
 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR       1
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 #endif
 #endif /* CONFIG_QE */
 
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index ae2fc19..9b81703 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -62,6 +62,12 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_L2_CACHE				/* toggle L2 cache	*/
 #define CONFIG_BTB				/* toggle branch predition */
 
+#ifdef CONFIG_MK_NAND
+#define CONFIG_NAND_U_BOOT		1
+#define CONFIG_RAMBOOT_NAND		1
+#define CONFIG_RAMBOOT_TEXT_BASE	0xf8f82000
+#endif
+
 /*
  * Only possible on E500 Version 2 or newer cores.
  */
@@ -74,16 +80,29 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_MEMTEST_END		0x00400000
 
 /*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+/*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR
 						/* physical addr of CCSRBAR */
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR
 						/* PQII uses CONFIG_SYS_IMMR */
 
+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSRBAR_DEFAULT	CONFIG_SYS_CCSRBAR
+#else
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#endif
+
 #define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
 
@@ -152,8 +171,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_BCSR_BASE_PHYS	CONFIG_SYS_BCSR_BASE
 
 /*Chip select 0 - Flash*/
-#define CONFIG_SYS_BR0_PRELIM		0xfe000801
-#define	CONFIG_SYS_OR0_PRELIM		0xfe000ff7
+#define CONFIG_FLASH_BR_PRELIM		0xfe000801
+#define	CONFIG_FLASH_OR_PRELIM		0xfe000ff7
 
 /*Chip select 1 - BCSR*/
 #define CONFIG_SYS_BR1_PRELIM		0xf8000801
@@ -175,12 +194,33 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
+#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 
 /* Chip select 3 - NAND */
+#ifndef CONFIG_NAND_SPL
 #define CONFIG_SYS_NAND_BASE		0xFC000000
+#else
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
+#endif
+
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START \
+	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
@@ -200,8 +240,18 @@ extern unsigned long get_clock_freq(void);
 				| OR_FCM_SCY_1 \
 				| OR_FCM_TRLX \
 				| OR_FCM_EHTR)
+
+#ifdef CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_NAND_BR_PRELIM	/* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_NAND_OR_PRELIM	/* NAND Options */
+#define CONFIG_SYS_BR3_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
 #define CONFIG_SYS_BR3_PRELIM	CONFIG_NAND_BR_PRELIM /* NAND Base Address */
 #define CONFIG_SYS_OR3_PRELIM	CONFIG_NAND_OR_PRELIM /* NAND Options */
+#endif
 
 /*
  * SDRAM on the LocalBus
@@ -326,12 +376,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR       7
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16	/* CLK16 for RMII */
 #define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR       8	/* 0x8 for RMII */
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 #endif /* CONFIG_UEC_ETH1 */
 
@@ -345,12 +397,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR       1
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16	/* CLK 16 for RMII */
 #define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR       0x9	/* 0x9 for RMII */
-#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 #endif /* CONFIG_UEC_ETH2 */
 
@@ -364,12 +418,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
 #define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC3_PHY_ADDR       2
-#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 #define CONFIG_SYS_UEC3_TX_CLK		QE_CLK16 /* CLK_16 for RMII */
 #define CONFIG_SYS_UEC3_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC3_PHY_ADDR	0xA     /* 0xA for RMII */
-#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 #endif /* CONFIG_UEC_ETH3 */
 
@@ -383,12 +439,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
 #define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC4_PHY_ADDR       3
-#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID
+#define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID
+#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
 #define CONFIG_SYS_UEC4_TX_CLK		QE_CLK16 /* CLK16 for RMII */
 #define CONFIG_SYS_UEC4_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC4_PHY_ADDR	0xB     /* 0xB for RMII */
-#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 #endif /* CONFIG_UEC_ETH4 */
 
@@ -401,7 +459,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
 #define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC6_PHY_ADDR       4
-#define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII
+#define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII
+#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
 #endif /* CONFIG_UEC_ETH6 */
 
 #undef CONFIG_UEC_ETH8         /* GETH8 */
@@ -413,7 +472,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
 #define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC8_PHY_ADDR       6
-#define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII
+#define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII
+#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
 #endif /* CONFIG_UEC_ETH8 */
 
 #endif /* CONFIG_QE */
@@ -437,10 +497,18 @@ extern unsigned long get_clock_freq(void);
 /*
  * Environment
  */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND	1
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
+#else
 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 256K(one sector) for env */
 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 6310cfc..89799af 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -287,12 +287,8 @@
 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 	"addmisc=setenv bootargs ${bootargs} mem=${mem}\0"		\
 	"nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
-	"nand_boot=run nandargs addip addtty addmisc;bootm ${kernel_addr}\0" \
 	"nand_boot_fdt=run nandargs addip addtty addmisc;"		\
 		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"run nfsargs addip addtty addmisc;"			\
-		"bootm\0"						\
 	"net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};"		\
 		"tftp  ${fdt_addr_r} ${fdt_file};"			\
 		"run nfsargs addip addtty addmisc;"			\
@@ -353,7 +349,6 @@
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
-#define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_FAT
@@ -366,7 +361,6 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
 
 /* POST support */
 #define CONFIG_POST		(CONFIG_SYS_POST_MEMORY |	\
diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h
index 58b8c8c..24484fd 100644
--- a/include/configs/afeb9260.h
+++ b/include/configs/afeb9260.h
@@ -26,8 +26,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		18429952	/* from 18.432 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK		18429952	/* from 18.432 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_AT91SAM9260	1	/* It's an Atmel AT91SAM9260 SoC*/
@@ -45,6 +47,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index 322718f..44c2870 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -27,8 +27,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
@@ -47,6 +49,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 590c69a..d39e8f2 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -25,6 +25,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 #define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
 #define AT91C_MASTER_CLOCK	59904000	/* peripheral clock (AT91C_MASTER_CLOCK / 3) */
@@ -122,7 +124,14 @@
 #define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END			CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
+
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_AT91C_USE_RMII
 
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index b4f075e..145c3c3 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -26,6 +26,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 /*
  * from 18.432 MHz crystal
@@ -145,7 +147,13 @@
 /*
  * Network Driver Setting
  */
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_AT91C_USE_RMII
 
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 0509011..b89242b 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -27,8 +27,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
@@ -52,6 +54,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index fbf7389..df8181b 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -27,8 +27,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
@@ -50,6 +52,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 571351c..5cafa1e 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -28,7 +28,7 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		16367660	/* 16.367 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	16367660	/* 16.367 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
@@ -49,6 +49,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
@@ -69,9 +70,9 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define	CONFIG_RED_LED		AT91_PIN_PB7	/* this is the power led */
-#define	CONFIG_GREEN_LED	AT91_PIN_PB8	/* this is the user1 led */
-#define	CONFIG_YELLOW_LED	AT91_PIN_PC29	/* this is the user2 led */
+#define	CONFIG_RED_LED		AT91_PIO_PORTB, 7	/* the power led */
+#define	CONFIG_GREEN_LED	AT91_PIO_PORTB, 8	/* the user1 led */
+#define	CONFIG_YELLOW_LED	AT91_PIO_PORTC, 29	/* the user2 led */
 
 #define CONFIG_BOOTDELAY	3
 
@@ -147,39 +148,36 @@
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #define MASTER_PLL_MUL		171
 #define MASTER_PLL_DIV		14
+#define MASTER_PLL_OUT		3
 
 /* clocks */
 #define CONFIG_SYS_MOR_VAL						\
-		(AT91_PMC_MOSCEN |					\
-		 (255 << 8))		/* Main Oscillator Start-up Time */
-#define CONFIG_SYS_PLLAR_VAL						\
-		(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
-		 AT91_PMC_OUT |						\
-		 AT91_PMC_PLLCOUNT |	/* PLL Counter */		\
-		 (2 << 28) |		/* PLL Clock Frequency Range */	\
-		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+		(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
+#define CONFIG_SYS_PLLAR_VAL					\
+	(AT91_PMC_PLLAR_29 |					\
+	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
+	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
+	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | 		\
+	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
 
 /* PCK/2 = MCK Master Clock from PLLA */
 #define	CONFIG_SYS_MCKR1_VAL		\
-		(AT91_PMC_CSS_SLOW |	\
-		 AT91_PMC_PRES_1 |	\
-		 AT91SAM9_PMC_MDIV_2 |	\
-		 AT91_PMC_PDIV_1)
+	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
+	 AT91_PMC_MCKR_MDIV_2)
+
 /* PCK/2 = MCK Master Clock from PLLA */
 #define	CONFIG_SYS_MCKR2_VAL		\
-		(AT91_PMC_CSS_PLLA |	\
-		 AT91_PMC_PRES_1 |	\
-		 AT91SAM9_PMC_MDIV_2 |	\
-		 AT91_PMC_PDIV_1)
+	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | 	\
+	AT91_PMC_MCKR_MDIV_2)
 
 /* define PDC[31:16] as DATA[31:16] */
 #define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
 /* no pull-up for D[31:16] */
 #define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
-#define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
-	(AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |	\
-	 AT91_MATRIX_EBI0_CS1A_SDRAMC)
+#define CONFIG_SYS_MATRIX_EBICSA_VAL					\
+	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
+	 AT91_MATRIX_CSA_EBI_CS1A)
 
 /* SDRAM */
 /* SDRAMC_MR Mode register */
@@ -221,33 +219,32 @@
 #define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
 
 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
-#define CONFIG_SYS_SMC0_SETUP0_VAL					\
-		(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |	\
-		 AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
-#define CONFIG_SYS_SMC0_PULSE0_VAL					\
-		(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |	\
-		 AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+#define CONFIG_SYS_SMC0_SETUP0_VAL				\
+	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
+	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL				\
+	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
+	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
 #define CONFIG_SYS_SMC0_CYCLE0_VAL	\
-		(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
 #define CONFIG_SYS_SMC0_MODE0_VAL				\
-		(AT91_SMC_READMODE | AT91_SMC_WRITEMODE |	\
-		 AT91_SMC_DBW_16 |				\
-		 AT91_SMC_TDFMODE |				\
-		 AT91_SMC_TDF_(6))
+	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
+	 AT91_SMC_MODE_DBW_16 |					\
+	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
 
 /* user reset enable */
 #define CONFIG_SYS_RSTC_RMR_VAL			\
 		(AT91_RSTC_KEY |		\
-		AT91_RSTC_PROCRST |		\
-		AT91_RSTC_RSTTYP_WAKEUP |	\
-		AT91_RSTC_RSTTYP_WATCHDOG)
+		AT91_RSTC_MR_URSTEN |		\
+		AT91_RSTC_MR_ERSTL(15))
 
 /* Disable Watchdog */
 #define CONFIG_SYS_WDTC_WDMR_VAL				\
-		(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |	\
-		 AT91_WDT_WDV |					\
-		 AT91_WDT_WDDIS |				\
-		 AT91_WDT_WDD)
+		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
+		 AT91_WDT_MR_WDV(0xfff) |			\
+		 AT91_WDT_MR_WDDIS |				\
+		 AT91_WDT_MR_WDD(0xfff))
+
 #endif
 
 #else
@@ -264,9 +261,15 @@
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 15
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTA, 22
+/*
+#define CONFIG_SYS_NAND_ENABLE_PIN  AT91_PIN_PD15
+#define CONFIG_SYS_NAND_READY_PIN  AT91_PIN_PA22
+*/
+
 
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
 #endif
 
 /* Ethernet */
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 06184e7..44c5496 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -27,8 +27,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		12000000	/* from 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* from 12 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
@@ -50,6 +52,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 6fad75d..e8fcd66 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -27,8 +27,10 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
@@ -47,6 +49,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index be478b2..ffe83f0 100644
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -25,6 +25,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 #define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
 #define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK/3)	/* peripheral clock */
@@ -152,7 +154,13 @@
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_AT91C_USE_RMII
 
diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h
index 4ef8566..fb6f79a 100644
--- a/include/configs/cpu9260.h
+++ b/include/configs/cpu9260.h
@@ -31,9 +31,11 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 #define CONFIG_DISPLAY_CPUINFO	1
 
-#define AT91_MAIN_CLOCK		18432000
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1
@@ -242,6 +244,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index 8746f70..b4fda76 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -26,6 +26,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 #ifdef CONFIG_CPUAT91_RAM
 #define CONFIG_SKIP_LOWLEVEL_INIT	1
 #define CONFIG_SKIP_RELOCATE_UBOOT	1
@@ -128,7 +130,13 @@
 #define CONFIG_SYS_MEMTEST_END			\
 	(CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512 * 1024)
 
-#define CONFIG_DRIVER_ETHER			1
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
 #define CONFIG_NET_RETRY_COUNT			20
 #define CONFIG_AT91C_USE_RMII			1
 #define CONFIG_PHY_ADDRESS			(1 << 5)
diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index f4fd808..efa2780 100644
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -26,6 +26,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 #define AT91C_MAIN_CLOCK	184320000	/* from 3.6864 MHz crystal (3686400 * 50) */
 #define AT91C_MASTER_CLOCK	46080000	/* (AT91C_MAIN_CLOCK/4)	peripheral clock */
@@ -126,7 +128,13 @@
 #define CONFIG_SYS_ALT_MEMTEST			1
 #define CONFIG_SYS_MEMTEST_SCRATCH		CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 4
 
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
 #define CONFIG_NET_RETRY_COUNT		20
 #undef CONFIG_AT91C_USE_RMII
 
diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h
index 432cd57..0f58e11 100644
--- a/include/configs/da830evm.h
+++ b/include/configs/da830evm.h
@@ -27,6 +27,7 @@
 /*
  * Board
  */
+#define CONFIG_DRIVER_TI_EMAC
 
 /*
  * SoC Configuration
@@ -103,14 +104,15 @@
 #define CONFIG_NAND_DAVINCI
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
-#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
-#define CONFIG_ENV_SIZE			(128 << 10)
+#define CONFIG_ENV_OFFSET		(512 << 10)
+#define CONFIG_ENV_SIZE			(512 << 10)
 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 #define CONFIG_SYS_NAND_CS		3
 #define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 #define CONFIG_SYS_CLE_MASK		0x10
 #define CONFIG_SYS_ALE_MASK		0x8
-#define CONFIG_SYS_NAND_HW_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
 #define NAND_MAX_CHIPS			1
 #define DEF_BOOTM			""
@@ -216,8 +218,7 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_UBI
-#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE
 #endif
 
 #ifdef CONFIG_USE_SPIFLASH
@@ -268,4 +269,15 @@
 #endif /* CONFIG_MUSB_UDC */
 
 #endif /* CONFIG_USB_DA8XX */
+
+#ifdef CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT		"nand0=davinci_nand.1"
+#define PART_BOOT		"512k(bootloader)ro,"
+#define PART_PARAMS		"512k(params)ro,"
+#define PART_KERNEL		"4m(kernel),"
+#define PART_REST		"-(filesystem)"
+#define MTDPARTS_DEFAULT        \
+	"mtdparts=davinci_nand.1:" PART_BOOT PART_PARAMS PART_KERNEL PART_REST
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h
index c6e1d10..6f99ae0 100644
--- a/include/configs/davinci_dm365evm.h
+++ b/include/configs/davinci_dm365evm.h
@@ -85,6 +85,44 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_MAX_CHIPS	2
 
+#define PINMUX4_USBDRVBUS_BITCLEAR       0x3000
+#define PINMUX4_USBDRVBUS_BITSET         0x2000
+
+/* USB Configuration */
+#define CONFIG_USB_DAVINCI
+#define CONFIG_MUSB_HCD
+
+#ifdef CONFIG_USB_DAVINCI
+#define CONFIG_CMD_USB         /* include support for usb      */
+#define CONFIG_CMD_STORAGE     /* include support for usb      */
+#define CONFIG_CMD_FAT         /* include support for FAT/storage*/
+#define CONFIG_DOS_PARTITION   /* include support for FAT/storage*/
+#endif
+
+#ifdef CONFIG_MUSB_HCD         /* include support for usb host */
+#define CONFIG_CMD_USB         /* include support for usb cmd */
+#define CONFIG_USB_STORAGE     /* MSC class support */
+#define CONFIG_CMD_STORAGE     /* inclue support for usb-storage cmd */
+#define CONFIG_CMD_FAT         /* inclue support for FAT/storage */
+#define CONFIG_DOS_PARTITION   /* inclue support for FAT/storage */
+
+#ifdef CONFIG_USB_KEYBOARD     /* HID class support */
+#define CONFIG_SYS_USB_EVENT_POLL
+
+#define CONFIG_PREBOOT "usb start"
+#endif /* CONFIG_USB_KEYBOARD */
+#endif /* CONFIG_MUSB_HCD */
+
+#ifdef CONFIG_MUSB_UDC
+#define CONFIG_USB_DEVICE              1
+#define CONFIG_USB_TTY                 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV   1
+#define CONFIG_USBD_VENDORID           0x0451
+#define CONFIG_USBD_PRODUCTID          0x5678
+#define CONFIG_USBD_MANUFACTURER       "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME       "DM365VM"
+#endif /* CONFIG_MUSB_UDC */
+
 /* U-Boot command configuration */
 #include <config_cmd_default.h>
 
diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
new file mode 100644
index 0000000..4ff4a85
--- /dev/null
+++ b/include/configs/eb_cpux9k2.h
@@ -0,0 +1,415 @@
+/*
+ * (C) Copyright 2008-2009
+ * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
+ * Jens Scharsig <esw@bus-elektronik.de>
+ *
+ * Configuation settings for the EB+CPUx9K2 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CONFIG_EB_CPUx9K2_H_
+#define _CONFIG_EB_CPUx9K2_H_
+
+/*--------------------------------------------------------------------------*/
+
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
+#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
+#define CONFIG_EB_CPUX9K2	1	/* on an EP+CPUX9K2 Board	*/
+#define USE_920T_MMU		1
+
+#define CONFIG_VERSION_VARIABLE 1
+#define CONFIG_IDENT_STRING	" on EB+CPUx9K2"
+
+#include <asm/arch/hardware.h>	/* needed for port definitions */
+
+#define CONFIG_MISC_INIT_R
+
+/*--------------------------------------------------------------------------*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
+
+#define CONFIG_SYS_BOOT_SIZE		0x00 /* 0 KBytes */
+#define CONFIG_SYS_U_BOOT_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_U_BOOT_SIZE		0x60000 /* 384 KBytes */
+
+
+#define CONFIG_BOOT_RETRY_TIME		30
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+/*
+ * ARM asynchronous clock
+ */
+
+#define AT91C_MAIN_CLOCK	179404800	/* from 12.288 MHz * 73 / 5 */
+#define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK / 3)
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_HZ_CLOCK 	(AT91C_MASTER_CLOCK / 2)
+
+#define AT91_SLOW_CLOCK			32768		/* slow clock */
+
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR	1
+/* flash */
+#define CONFIG_SYS_EBI_CFGR_VAL		0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL		0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define CONFIG_SYS_PLLAR_VAL		0x20483E05 /* 179.4048 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL		0x104C3E0A /* 47.3088 MHz (for USB) */
+#define CONFIG_SYS_MCKR_VAL		0x00000202 /* PCK/3 = MCK Clock */
+
+/*
+ * Size of malloc() pool
+ */
+
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 520*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * sdram
+ */
+
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM 			0x20000000
+#define PHYS_SDRAM_SIZE			0x04000000  /* 64 megs */
+
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					PHYS_SDRAM_SIZE - 0x00400000 - \
+					CONFIG_SYS_MALLOC_LEN)
+
+#define CONFIG_SYS_PIOC_ASR_VAL		0xFFFF0000 /* PIOC as D16/D31 */
+#define CONFIG_SYS_PIOC_BSR_VAL		0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL		0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL		0x00000002 /* CS1=SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL		0x2188c159 /* set up the SDRAM */
+#define CONFIG_SYS_SDRAM		0x20000000 /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM1		0x20000080 /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM_VAL		0x00000000 /* value written to SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL		0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1		0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2		0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3		0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL		0x000002E0 /* Write refresh rate */
+
+/*
+ * Command line configuration
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_I2C_CMD_NO_FLAT
+#define CONFIG_I2C_CMD_TREE
+
+#define CONFIG_SYS_LONGHELP
+
+/*
+ * Filesystems
+ */
+
+#define CONFIG_JFFS2_NAND		1
+
+#ifndef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV 		"nand0"
+#define CONFIG_JFFS2_PART_OFFSET 	0
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#else
+#define MTDIDS_DEFAULT		"nor0=0,nand0=1"
+#define MTDPARTS_DEFAULT	"mtdparts="				\
+					"0:"				\
+					"384k(U-Boot),"			\
+					"128k(Env),"			\
+					"128k(Splash)," 		\
+					"4M(Kernel),"			\
+					"-(FS)"				\
+					";"				\
+					"1:"				\
+					"-(jffs2)"
+#endif /* CONFIG_JFFS2_CMDLINE */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * UART/CONSOLE
+ */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 19200, 38400, 57600, 9600 }
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AT91RM9200_USART
+#define CONFIG_DBGU			/* define DBGU as console */
+
+/*
+ * network
+ */
+#define CONFIG_NET_MULTI		1
+
+#define CONFIG_NET_RETRY_COUNT		10
+#define CONFIG_RESET_PHY_R		1
+
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_DRIVER_AT91EMAC_QUIET	1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#define CONFIG_MII			1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * I2C-Bus
+ */
+
+#define CONFIG_SYS_I2C_SPEED		50000
+#define CONFIG_SYS_I2C_SLAVE		0 		/* not used */
+
+#ifndef CONFIG_HARD_I2C
+#define CONFIG_SOFT_I2C
+
+/* Software  I2C driver configuration */
+
+#define AT91_PIN_SDA			(1<<25)		/* AT91C_PIO_PA25 */
+#define AT91_PIN_SCL			(1<<26)		/* AT91C_PIO_PA26 */
+
+#define CONFIG_SYS_I2C_INIT_BOARD
+
+#define I2C_INIT	i2c_init_board();
+#define I2C_ACTIVE	writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
+#define I2C_TRISTATE	writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
+#define I2C_READ	((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
+#define I2C_SDA(bit)						\
+	if (bit)						\
+		writel(AT91_PMX_AA_TWD, &pio->pioa.sodr);	\
+	else							\
+		writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
+#define I2C_SCL(bit)						\
+	if (bit)						\
+		writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr);	\
+	else							\
+		writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
+
+#define I2C_DELAY	udelay(2500000/CONFIG_SYS_I2C_SPEED)
+
+#endif	/* CONFIG_HARD_I2C */
+
+/* I2C-RTC */
+
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1338
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#endif
+
+/* EEPROM */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+
+/* FLASH organization */
+
+/*  NOR-FLASH */
+
+#define CONFIG_FLASH_CFI_DRIVER	1
+
+#define PHYS_FLASH_1			0x10000000
+#define PHYS_FLASH_SIZE			0x01000000  /* 16 megs main flash */
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_PROTECTION	1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_FLASH_ERASE_TOUT	6000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	2000
+
+/* NAND */
+
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8		1
+
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+
+/* Status LED's */
+
+#define CONFIG_STATUS_LED		1
+#define CONFIG_BOARD_SPECIFIC_LED	1
+
+#define STATUS_LED_BOOT			1
+#define STATUS_LED_ACTIVE		0
+
+#define STATUS_LED_BIT			1	/* AT91C_PIO_PD0 green LED */
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_STATE 		STATUS_LED_OFF		/* BLINKING */
+#define STATUS_LED_BIT1			2	/* AT91C_PIO_PD1  red LED */
+#define STATUS_LED_STATE1		STATUS_LED_ON		/* BLINKING */
+#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 4)
+
+#define	CONFIG_VIDEO			1
+
+/* Options */
+
+#ifdef CONFIG_VIDEO
+
+#define CONFIG_VIDEO_VCXK			1
+
+#define CONFIG_SPLASH_SCREEN			1
+
+#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN	4
+#define CONFIG_SYS_VCXK_BASE	0x30000000
+
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN		(1<<3)
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT	piob
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR		odr
+
+#define CONFIG_SYS_VCXK_ENABLE_PIN		(1<<5)
+#define CONFIG_SYS_VCXK_ENABLE_PORT		piob
+#define CONFIG_SYS_VCXK_ENABLE_DDR		oer
+
+#define CONFIG_SYS_VCXK_REQUEST_PIN		(1<<2)
+#define CONFIG_SYS_VCXK_REQUEST_PORT		piob
+#define CONFIG_SYS_VCXK_REQUEST_DDR		oer
+
+#define CONFIG_SYS_VCXK_INVERT_PIN		(1<<4)
+#define CONFIG_SYS_VCXK_INVERT_PORT		piob
+#define CONFIG_SYS_VCXK_INVERT_DDR		oer
+
+#define CONFIG_SYS_VCXK_RESET_PIN		(1<<6)
+#define CONFIG_SYS_VCXK_RESET_PORT		piob
+#define CONFIG_SYS_VCXK_RESET_DDR		oer
+
+#endif	/* CONFIG_VIDEO */
+
+/* Environment */
+
+#define CONFIG_BOOTDELAY		5
+
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x60000)
+#define CONFIG_ENV_SIZE			0x20000 /* sectors are 128K here */
+
+#define CONFIG_BAUDRATE 		115200
+
+#define CONFIG_BOOTCOMMAND		"run nfsboot"
+
+#define CONFIG_NFSBOOTCOMMAND 						\
+		"dhcp $(copy_addr) uImage_cpux9k2;"			\
+		"run bootargsdefaults;"					\
+		"set bootargs $(bootargs) boot=nfs "			\
+		";echo $(bootargs)"					\
+	";bootm"
+
+#define CONFIG_EXTRA_ENV_SETTINGS 					\
+	"displaywidth=256\0"						\
+	"displayheight=512\0"						\
+	"displaybsteps=1023\0"						\
+	"ubootaddr=10000000\0"						\
+	"splashimage=10080000\0"					\
+	"kerneladdr=100A0000\0"						\
+	"kernelsize=00400000\0"						\
+	"rootfsaddr=104A0000\0"						\
+	"copy_addr=21200000\0"						\
+	"rootfssize=00B60000\0"						\
+	"bootargsdefaults=set bootargs "				\
+		"console=ttyS0,115200 "					\
+		"video=vcxk_fb:xres:${displaywidth},"			\
+			"yres:${displayheight},"			\
+			"bres:${displaybsteps} "			\
+		"mem=62M "						\
+		"panic=10 "						\
+		"uboot=\\\"${ver}\\\" "					\
+		"\0"							\
+	"update_kernel=protect off $(kerneladdr) +$(kernelsize);"	\
+		"dhcp $(copy_addr) uImage_cpux9k2;"			\
+		"erase $(kerneladdr) +$(kernelsize);"			\
+		"cp.b $(fileaddr) $(kerneladdr) $(filesize);"		\
+		"protect on $(kerneladdr) +$(kernelsize)"		\
+		"\0"							\
+	"update_root=protect off $(rootfsaddr) +$(rootfssize);"		\
+		"dhcp $(copy_addr) rfs;"				\
+		"erase $(rootfsaddr) +$(rootfssize);"			\
+		"cp.b $(fileaddr) $(rootfsaddr) $(filesize);"		\
+		"\0"							\
+	"update_uboot=protect off 10000000 1005FFFF;"			\
+		"dhcp $(copy_addr) u-boot_eb_cpux9k2;"			\
+		"erase 10000000 1005FFFF;"				\
+		"cp.b $(fileaddr) $(ubootaddr) $(filesize);"		\
+		"protect on 10000000 1005FFFF;reset\0"			\
+	"update_splash=protect off $(splashimage) +20000;"		\
+		"dhcp $(copy_addr) splash_eb_cpux9k2.bmp;"		\
+		"erase $(splashimage) +20000;"				\
+		"cp.b $(fileaddr) 10080000 $(filesize);"		\
+		"protect on $(splashimage) +20000;reset\0"		\
+	"emergency=run bootargsdefaults;"				\
+		"set bootargs $(bootargs) root=initramfs boot=emergency " \
+		";bootm $(kerneladdr)\0"				\
+	"netemergency=run bootargsdefaults;"				\
+		"dhcp $(copy_addr) uImage_cpux9k2;"			\
+		"set bootargs $(bootargs) root=initramfs boot=emergency " \
+		";bootm $(copy_addr)\0"					\
+	"norboot=run bootargsdefaults;"					\
+		"set bootargs $(bootargs) root=initramfs boot=local "	\
+		";bootm $(kerneladdr)\0"				\
+	"nandboot=run bootargsdefaults;"				\
+		"set bootargs $(bootargs) root=initramfs boot=nand "	\
+		";bootm $(kerneladdr)\0"				\
+	"uu=run update_uboot\0"						\
+	"ur=run update_root;run nk\0"					\
+	"nk=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \
+		"boot=local "						\
+		";echo $(bootargs)"					\
+		";dhcp uImage_cpux9k2;bootm\0"				\
+	"nn=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \
+		"boot=nand "						\
+		";echo $(bootargs)"					\
+		";dhcp uImage_cpux9k2;bootm\0"				\
+	" "
+
+/*--------------------------------------------------------------------------*/
+
+#endif
+
+/* EOF */
diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h
index 7dd81e6..41ec1d5 100644
--- a/include/configs/kb9202.h
+++ b/include/configs/kb9202.h
@@ -29,6 +29,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 #define AT91C_MAIN_CLOCK	180000000	/* from 10 MHz crystal */
 #define AT91C_MASTER_CLOCK	60000000	/* peripheral clock (AT91C_MASTER_CLOCK / 3) */
@@ -115,7 +117,13 @@
 #define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END			CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - (512*1024)
 
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
 #define CONFIG_NET_RETRY_COUNT		20
 
 #define CONFIG_SYS_FLASH_BASE			0x10000000
diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h
new file mode 100644
index 0000000..a928c2c
--- /dev/null
+++ b/include/configs/km_arm.h
@@ -0,0 +1,191 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* for linking errors see http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
+
+#ifndef _CONFIG_KM_ARM_H
+#define _CONFIG_KM_ARM_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL
+#define CONFIG_ARM926EJS		/* Basic Architecture */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KIRKWOOD			/* SOC Family Name */
+#define CONFIG_KW88F6281		/* SOC Name */
+#define CONFIG_MACH_SUEN3		/* Machine type */
+
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
+#undef CONFIG_CMD_DTT
+#undef CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
+#undef  CONFIG_KIRKWOOD_PCIE_INIT	/* Disable PCIE Port0 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX	1	/* Console on UART0 */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_BOOTMAPSZ	(8 << 20)	/* Initial Memmap for Linux */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG		/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 	/* enable memory tag */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+
+/*
+ * Without NOR FLASH we need this
+ */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+
+/*
+ * NAND Flash configuration
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_NAND_BASE		0xd8000000
+
+#define BOOTFLASH_START		0x0
+
+#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
+
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET	/* some code reduction */
+#define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT		/* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO		/* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS	4
+#define CONFIG_STACKSIZE	0x00100000	/* regular stack- 1M */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+
+/*
+ * Ethernet Driver configuration
+ */
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_NET_MULTI	/* specify more that one ports available */
+#define CONFIG_MII		/* expose smi ove miiphy interface */
+#define CONFIG_KIRKWOOD_EGIGA	/* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_KIRKWOOD_EGIGA_PORTS	{1,0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R	/* use reset_phy() to init 88E1118 PHY */
+
+/*
+ * UBI related stuff
+ */
+#define CONFIG_SYS_USE_UBI
+
+/*
+ * I2C related stuff
+ */
+#undef	CONFIG_HARD_I2C		/* I2C with hardware support */
+#define	CONFIG_SOFT_I2C		/* I2C bit-banged	*/
+
+#if defined(CONFIG_HARD_I2C)
+#define	CONFIG_I2C_KIRKWOOD
+#define	CONFIG_I2C_KW_REG_BASE		KW_TWSI_BASE
+#define	CONFIG_SYS_I2C_SLAVE		0x0
+#define	CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#define	CONFIG_KIRKWOOD_GPIO		/* Enable GPIO Support */
+#if defined(CONFIG_SOFT_I2C)
+#ifndef __ASSEMBLY__
+#include <asm/arch-kirkwood/gpio.h>
+extern void __set_direction(unsigned pin, int high);
+void set_sda (int state);
+void set_scl (int state);
+int get_sda (void);
+int get_scl (void);
+#define SUEN3_SDA_PIN	8
+#define SUEN3_SCL_PIN	9
+#define SUEN3_ENV_WP	38
+
+#define I2C_ACTIVE	__set_direction(SUEN3_SDA_PIN, 0)
+#define I2C_TRISTATE	__set_direction(SUEN3_SDA_PIN, 1)
+#define I2C_READ	(kw_gpio_get_value(SUEN3_SDA_PIN) ? 1 : 0)
+#define I2C_SDA(bit)	kw_gpio_set_value(SUEN3_SDA_PIN, bit);
+#define I2C_SCL(bit)	kw_gpio_set_value(SUEN3_SCL_PIN, bit);
+#endif
+
+#define I2C_DELAY	udelay(3)	/* 1/4 I2C clock duration */
+#define I2C_SOFT_DECLARATIONS
+
+#define	CONFIG_SYS_I2C_SLAVE		0x0
+#define	CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+#if defined(CONFIG_SYS_NO_FLASH)
+#define CONFIG_KM_UBI_PARTITION_NAME   "ubi0"
+#undef	CONFIG_FLASH_CFI_MTD
+#undef	CONFIG_JFFS2_CMDLINE
+#endif
+
+#endif /* _CONFIG_KM_ARM_H */
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 0327b97..d27b75b 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -295,7 +295,8 @@
 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR	0
-#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 #endif
 
 /*
diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h
index 5c06642..26c2bcb 100644
--- a/include/configs/m501sk.h
+++ b/include/configs/m501sk.h
@@ -27,6 +27,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
 #define AT91C_MAIN_CLOCK	179712000
@@ -34,6 +36,7 @@
 #define AT91C_MASTER_CLOCK	59904000
 #define AT91_SLOW_CLOCK	32768 /* slow clock */
 
+#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
 #define CONFIG_AT91RM9200DK	1 /* on an AT91RM9200DK Board    */
 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
 #define CONFIG_CMDLINE_TAG	1 /* enable passing of ATAGs    */
@@ -166,7 +169,13 @@
 /* CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */
 #define CONFIG_SYS_MEMTEST_END	0x00100000
 
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
 #define CONFIG_NET_RETRY_COUNT	20
 #define CONFIG_AT91C_USE_RMII
 
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index c3255fa..d002b97 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -31,6 +31,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* Common stuff */
 #define CONFIG_SYS_HZ			1000	/* decrementer freq */
 #define CONFIG_MEESC			1	/* Board is esd MEESC */
@@ -57,6 +59,7 @@
  */
 
 /* Console output */
+#define CONFIG_AT91_GPIO			1
 #define CONFIG_ATMEL_USART			1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index 0c2ee60..3138b49 100644
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -28,6 +28,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 #define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 45) */
 #define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK/3)	/* peripheral clock */
@@ -181,7 +183,13 @@
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 
-#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_MULTI		1
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#else
+#define CONFIG_DRIVER_ETHER		1
+#endif
 #define CONFIG_NET_RETRY_COUNT		20
 #undef CONFIG_AT91C_USE_RMII
 
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
new file mode 100644
index 0000000..903fe6d
--- /dev/null
+++ b/include/configs/mx51evk.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51EVK Board
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+ /* High Level Configuration Options */
+
+#define CONFIG_MX51	/* in a mx51 */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_MX51_HCLK_FREQ		24000000	/* RedBoot says 26MHz */
+#define CONFIG_MX51_CLK32		32768
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_L2_OFF
+
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX51_UART1
+
+/*
+ * MMC Configs
+ * */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+
+#define CONFIG_MMC
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_PRIME	"FEC0"
+
+#define CONFIG_LOADADDR		0x90800000	/* loadaddr env var */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+		"netdev=eth0\0"						\
+		"uboot_addr=0xa0000000\0"				\
+		"uboot=u-boot.bin\0"			\
+		"loadaddr=0x90800000\0"			\
+		"bootargs_base=setenv bootargs console=tty "\
+			"console=ttymxc0,${baudrate}\0"\
+		"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+			"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+		"bootcmd=run bootcmd_net\0"				\
+		"bootcmd_net=run bootargs_base bootargs_nfs; "		\
+			"tftpboot ${loadaddr} ${kernel}; bootm\0"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"MX51EVK U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x90000000
+#define CONFIG_SYS_MEMTEST_END         0x10000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_CMDLINE_EDITING
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SECT_SIZE    (128 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_IS_NOWHERE
+
+#endif
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index 884dc09..c63c846 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -27,17 +27,13 @@
 
 #include <configs/omap1510.h>
 
-/*
- * High Level Configuration Options
- * (easy to change)
- */
 #define CONFIG_ARM925T	1		/* This is an arm925t CPU */
 #define CONFIG_OMAP	1		/* in a TI OMAP core */
 #define CONFIG_OMAP1510 1		/* which is in a 5910 */
 
 /* Input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	150000000	/* 150MHz input clock */
-#define CONFIG_XTAL_FREQ	12000000
+#define CONFIG_SYS_CLK_FREQ		150000000	/* 150MHz */
+#define CONFIG_XTAL_FREQ		12000000	/*  12MHz */
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
@@ -54,10 +50,10 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	(64 * 1024 * 1024)
-#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1 */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x10000000
+#define PHYS_SDRAM_1_SIZE		(64 * 1024 * 1024)
+#define PHYS_FLASH_1			0x00000000
 
 #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
@@ -66,23 +62,23 @@
  * Environment settings
  */
 #define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR		0x4000
-#define CONFIG_ENV_SIZE		(8 * 1024)
-#define CONFIG_ENV_SECT_SIZE	(8 * 1024)
-#define CONFIG_ENV_ADDR_REDUND	0x6000
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+#define CONFIG_ENV_ADDR			0x4000
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(8 * 1024)
+#define CONFIG_ENV_ADDR_REDUND		0x6000
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
 #define CONFIG_ENV_OVERWRITE
 
 /*
  * Size of malloc() pool
  */
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 
 /*
  * The stack size is set up in start.S using the settings below
  */
-#define CONFIG_STACKSIZE	(1 * 1024 * 1024)	/* regular stack */
+#define CONFIG_STACKSIZE		(1 * 1024 * 1024)
 
 /*
  * Hardware drivers
@@ -90,8 +86,8 @@
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		(CONFIG_XTAL_FREQ)	/* can be 12M/32Khz or 48Mhz  */
-#define CONFIG_SYS_NS16550_COM1		OMAP1510_UART1_BASE	/* uart1 */
+#define CONFIG_SYS_NS16550_CLK		(CONFIG_XTAL_FREQ)
+#define CONFIG_SYS_NS16550_COM1		OMAP1510_UART1_BASE
 
 #define CONFIG_NET_MULTI
 #define CONFIG_SMC91111
@@ -128,19 +124,18 @@
 /*#define CONFIG_SKIP_LOWLEVEL_INIT */
 
 /*
- * partitions (mtdparts command line support)
+ * Partitions (mtdparts command line support)
  */
 #define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_MTD_DEVICE
 #define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=omapflash.0,nand0=omapnand.0"
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=gen_nand.0"
 #define MTDPARTS_DEFAULT	"mtdparts=" \
-	"omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \
-	"omapnand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)"
-
+	"physmap-flash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \
+	"gen_nand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)"
 
 /*
- * Command line configuration.
+ * Command line configuration
  */
 #define CONFIG_CMD_BDI
 #define CONFIG_CMD_BOOTD
@@ -156,7 +151,6 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_RUN
 
-
 /*
  * BOOTP options
  */
@@ -173,26 +167,27 @@
 #define CONFIG_SYS_AUTOLOAD		"n"		/* No autoload */
 #define CONFIG_BOOTCOMMAND	"run fboot"
 #define CONFIG_PREBOOT		"run setup"
-#define	CONFIG_EXTRA_ENV_SETTINGS						\
-	"autostart=yes\0"							\
-	"ospart=0\0"								\
-	"setup=setenv bootargs console=ttyS0,$baudrate "			\
-		"$mtdparts\0"							\
-	"setpart="								\
-	"if test -n $swapos; then "						\
-		"setenv swapos; saveenv; "					\
-	"else "									\
-		"if test $ospart -eq 0; then setenv ospart 1;"			\
-			"else setenv ospart 0;		fi; "			\
-	"fi\0"									\
-	"nfsargs=setenv bootargs $bootargs "					\
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off "	\
-		"nfsroot=$rootpath root=/dev/nfs\0"				\
-	"flashargs=run setpart;setenv bootargs $bootargs "			\
-		"root=mtd:rootfs$ospart ro "					\
-		"rootfstype=jffs2\0"						\
-	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0"		\
-	"fboot=run flashargs;nboot kernel$ospart\0"				\
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"autostart=yes\0"						\
+	"ospart=0\0"							\
+	"setup=setenv bootargs console=ttyS0,$baudrate $mtdparts\0"	\
+	"setpart="							\
+	"if test -n $swapos; then "					\
+		"setenv swapos; saveenv; "				\
+		"if test $ospart -eq 0; then "				\
+			"setenv ospart 1; "				\
+		"else "							\
+			"setenv ospart 0; "				\
+		"fi; "							\
+	"fi\0"								\
+	"nfsargs=setenv bootargs $bootargs "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
+		"nfsroot=$rootpath root=/dev/nfs\0"			\
+	"flashargs=run setpart;setenv bootargs $bootargs "		\
+		"root=mtd:rootfs$ospart ro "				\
+		"rootfstype=jffs2\0"					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0"	\
+	"fboot=run flashargs;nboot kernel$ospart\0"			\
 	"nboot=bootp;run nfsargs;tftp\0"
 
 #if 0	/* feel free to disable for development */
@@ -205,12 +200,13 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"# "		/* Monitor Command Prompt	*/
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"# "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+	 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
@@ -218,9 +214,9 @@
 
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
 #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
-				(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)
+	(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)
 
-#define CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1 + 0x400000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		(PHYS_SDRAM_1 + 0x400000)
 
 /* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
  * This time is further subdivided by a local divisor.
@@ -229,9 +225,9 @@
 #define CONFIG_SYS_PTV			7
 #define CONFIG_SYS_HZ			1000
 
-#define OMAP5910_DPLL_DIV	1
-#define OMAP5910_DPLL_MUL	((CONFIG_SYS_CLK_FREQ * \
-				 (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
+#define OMAP5910_DPLL_DIV		1
+#define OMAP5910_DPLL_MUL		\
+	((CONFIG_SYS_CLK_FREQ * (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
 
 #define OMAP5910_ARM_PER_DIV	2	/* CKL/4 */
 #define OMAP5910_LCD_DIV	2	/* CKL/4 */
@@ -241,7 +237,7 @@
 #define OMAP5910_DSP_MMU_DIV	1	/* CKL/2 */
 #define OMAP5910_ARM_TIM_SEL	1	/* CKL used for MPU timers */
 
-#define OMAP5910_ARM_EN_CLK	0x03d6	/* 0000 0011 1101 0110b  Clock Enable */
+#define OMAP5910_ARM_EN_CLK	0x03d6	/* 0000 0011 1101 0110b */
 #define OMAP5910_ARM_CKCTL	((OMAP5910_ARM_PER_DIV)  |	\
 				 (OMAP5910_LCD_DIV << 2) |	\
 				 (OMAP5910_ARM_DIV << 4) |	\
diff --git a/include/configs/otc570.h b/include/configs/otc570.h
index bedaf13..8e27eba 100644
--- a/include/configs/otc570.h
+++ b/include/configs/otc570.h
@@ -55,6 +55,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO		1
 
 /* Console output */
 #define CONFIG_ATMEL_USART		1
@@ -96,24 +97,22 @@
 #ifdef CONFIG_SOFT_I2C
 #define CONFIG_I2C_CMD_TREE		1
 #define CONFIG_I2C_MULTI_BUS		1
-/* Enable peripheral clock and configure data and clock pins for pio */
+/* Configure data and clock pins for pio */
 #define I2C_INIT { \
-	at91_sys_write(AT91_PMC_PCER,	1 << AT91SAM9263_ID_PIOB |	\
-					1 << AT91SAM9263_ID_PIOCDE);	\
-	at91_set_gpio_output(AT91_PIN_PB4, 0);				\
-	at91_set_gpio_output(AT91_PIN_PB5, 0);				\
+	at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \
+	at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \
 }
 /* Configure data pin as output */
-#define I2C_ACTIVE			at91_set_gpio_output(AT91_PIN_PB4, 0)
+#define I2C_ACTIVE		at91_set_pio_output(AT91_PIO_PORTB, 4, 0)
 /* Configure data pin as input */
-#define I2C_TRISTATE			at91_set_gpio_input(AT91_PIN_PB4, 0)
+#define I2C_TRISTATE		at91_set_pio_input(AT91_PIO_PORTB, 4, 0)
 /* Read data pin */
-#define I2C_READ			at91_get_gpio_value(AT91_PIN_PB4)
+#define I2C_READ		at91_get_pio_value(AT91_PIO_PORTB, 4)
 /* Set data pin */
-#define I2C_SDA(bit)			at91_set_gpio_value(AT91_PIN_PB4, bit)
+#define I2C_SDA(bit)		at91_set_pio_value(AT91_PIO_PORTB, 4, bit)
 /* Set clock pin */
-#define I2C_SCL(bit)			at91_set_gpio_value(AT91_PIN_PB5, bit)
-#define I2C_DELAY			udelay(2) /* 1/4 I2C clock duration */
+#define I2C_SCL(bit)		at91_set_pio_value(AT91_PIO_PORTB, 5, bit)
+#define I2C_DELAY		udelay(2) /* 1/4 I2C clock duration */
 #endif /* CONFIG_SOFT_I2C */
 
 #define CONFIG_BOOTDELAY		3
@@ -173,8 +172,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTD, 15
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 22
 #define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
 #endif
 
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 399d15f..47bb8c0 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -28,15 +28,17 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
-#define AT91_CPU_NAME		"AT91SAM9261"
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9261"
 
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define MASTER_PLL_DIV		15
 #define MASTER_PLL_MUL		162
 #define MAIN_PLL_DIV		2
-#define AT91_MAIN_CLOCK		18432000
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
 
 #define CONFIG_SYS_HZ		1000
 
@@ -157,6 +159,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 0af1280..807dba8 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -28,6 +28,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 /* ARM asynchronous clock */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -35,7 +37,7 @@
 #define MASTER_PLL_DIV		6
 #define MASTER_PLL_MUL		65
 #define MAIN_PLL_DIV		2	/* 2 or 4 */
-#define AT91_MAIN_CLOCK	18432000
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
 
 #define CONFIG_SYS_HZ		1000
 
@@ -171,6 +173,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h
index f4b3477..b9f27cc 100644
--- a/include/configs/sbc35_a9g20.h
+++ b/include/configs/sbc35_a9g20.h
@@ -26,6 +26,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 #if defined(CONFIG_SBC35_A9G20_NANDFLASH) || defined(CONFIG_SBC35_A9G20_EEPROM)
 #define CONFIG_SBC35_A9G20
 #endif
@@ -39,7 +41,7 @@
 #endif
 
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		12000000	/* 12.000 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12.000 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
@@ -57,6 +59,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART
 #define CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 7bef119..4ea65ce 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -631,21 +631,13 @@
 
 #if defined(CONFIG_TSEC_ENET)
 #define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR		00:a0:1e:a0:13:8d
 #define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR		00:a0:1e:a0:13:8e
 #endif
 
-#define CONFIG_IPADDR		192.168.1.234
-
 #define CONFIG_HOSTNAME		SBC8349
 #define CONFIG_ROOTPATH		/tftpboot/rootfs
 #define CONFIG_BOOTFILE		uImage
 
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.255.0
-
 #define CONFIG_LOADADDR		800000	/* default location for tftp and bootm */
 
 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
diff --git a/include/configs/suen3.h b/include/configs/suen3.h
new file mode 100644
index 0000000..b2730a3
--- /dev/null
+++ b/include/configs/suen3.h
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * for linking errors see
+ * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
+ */
+
+#ifndef _CONFIG_SUEN3_H
+#define _CONFIG_SUEN3_H
+
+/* include common defines/options for all arm based Keymile boards */
+#include "km_arm.h"
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nKeymile SUEN3"
+
+#define CONFIG_HOSTNAME			suen3
+
+/*
+ *  Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_EEPROM		/* use EEPROM for environment vars */
+#define CONFIG_SYS_DEF_EEPROM_ADDR	0x50
+#define CONFIG_ENV_EEPROM_IS_ON_I2C	1
+#define CONFIG_SYS_EEPROM_WREN		1
+#define CONFIG_ENV_OFFSET		0x0 /* no bracets! */
+#undef	CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE			(0x2000 - CONFIG_ENV_OFFSET)
+#define CONFIG_I2C_ENV_EEPROM_BUS	"pca9547:70:d\0"
+
+/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND	0x2000 /* no bracets! */
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+
+#define CONFIG_CMD_SF
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_HARD_SPI
+#define CONFIG_KIRKWOOD_SPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		50000000	/* 50Mhz */
+
+#define FLASH_GPIO_PIN			0x00010000
+
+#define MTDIDS_DEFAULT		"nand0=orion_nand"
+/* test-only: partitioning needs some tuning, this is just for tests */
+#define MTDPARTS_DEFAULT	"mtdparts="				\
+	"orion_nand:"							\
+		"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+
+#define	CONFIG_KM_DEF_ENV_UPDATE					\
+	"update="							\
+		"spi on;sf probe 0;sf erase 0 50000;"			\
+		"sf write ${u-boot_addr_r} 0 ${filesize};"		\
+		"spi off\0"
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_DEF_ENV						\
+	"memsize=0x8000000\0"						\
+	"newenv=setenv addr 0x100000 && "				\
+		"i2c dev 1; mw.b ${addr} 0 4 && "			\
+		"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)	\
+		" ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && "		\
+		"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR)	\
+		" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"	\
+	"rootpath=/opt/eldk/arm\0"					\
+	"EEprom_ivm=pca9544a:70:9\0"					\
+	""
+
+#endif /* _CONFIG_SUEN3_H */
diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h
index 4ad081b..5af2af3 100644
--- a/include/configs/tny_a9260.h
+++ b/include/configs/tny_a9260.h
@@ -30,6 +30,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_AT91_LEGACY
+
 #if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9260_EEPROM)
 #define CONFIG_TNY_A9260
 #elif defined(CONFIG_TNY_A9G20_NANDFLASH) || defined(CONFIG_TNY_A9G20_EEPROM)
@@ -49,7 +51,7 @@
 #endif
 
 /* ARM asynchronous clock */
-#define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core */
@@ -66,6 +68,7 @@
 /*
  * Hardware drivers
  */
+#define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
 #undef CONFIG_USART0
 #undef CONFIG_USART1
diff --git a/include/configs/tx25.h b/include/configs/tx25.h
new file mode 100644
index 0000000..c8188ca
--- /dev/null
+++ b/include/configs/tx25.h
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+/*
+ * KARO TX25 board - SoC Configuration
+ */
+#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
+#define CONFIG_MX25
+#define CONFIG_TX25
+#define CONFIG_MX25_CLK32		32000	/* OSC32K frequency */
+#define CONFIG_SYS_HZ			1000
+
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* 256 kB for U-Boot */
+
+/* NAND BOOT is the only boot method */
+#define CONFIG_NAND_U_BOOT
+
+#ifdef CONFIG_NAND_SPL
+/* Start copying real U-boot from the second page */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x800
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x30000
+/* Load U-Boot to this address */
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x81f00000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_SPARE_SIZE	64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_SIZE		(128 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#else
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#endif
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Memory Info
+ */
+/* malloc() len */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
+/* reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+/*
+ * Board has 2 32MB banks of DRAM but there is a bug when using
+ * both so only the first is configured
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+
+#define PHYS_SDRAM_1		0x80000000
+#define PHYS_SDRAM_1_SIZE	0x02000000
+#if (CONFIG_NR_DRAM_BANKS == 2)
+#define PHYS_SDRAM_2		0x90000000
+#define PHYS_SDRAM_2_SIZE	0x02000000
+#endif
+/* 8MB DRAM test */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1+0x0800000)
+#define CONFIG_STACKSIZE	(256 * 1024)	/* regular stack */
+
+/*
+ * Serial Info
+ */
+#define CONFIG_MXC_UART		1
+#define CONFIG_SYS_MX25_UART1	1
+#define CONFIG_CONS_INDEX	1	/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200	/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Flash & Environment
+ */
+/* No NOR flash present */
+#define CONFIG_SYS_NO_FLASH	1
+#define	CONFIG_ENV_IS_IN_NAND
+#define	CONFIG_ENV_OFFSET	CONFIG_SYS_MONITOR_LEN
+#define CONFIG_ENV_SIZE		(128 * 1024)	/* 128 kB NAND block size */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+
+/* NAND */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE	(0xBB000000)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(0xBB000000)
+#define CONFIG_JFFS2_NAND
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
+/* Print buffer sz */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+		sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	32	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+/* U-Boot commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_NAND
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0x1f
+#define CONFIG_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+#define BOARD_LATE_INIT
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_LOADADDR		0x81000000	/* loadaddr env var */
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc0,${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"u-boot=tx25/u-boot.bin\0"					\
+	"kernel_addr_r=" xstr(CONFIG_LOADADDR) "\0"			\
+	"hostname=tx25\0"						\
+	"bootfile=tx25/uImage\0"					\
+	"rootpath=/opt/eldk/arm\0"					\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm\0"						\
+	"bootcmd=run net_nfs\0"						\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0"	\
+	"upd=run load update\0"						\
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index dbc15b2..7603300 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -118,7 +118,7 @@
 #define CONFIG_SYS_FLASH_BASE		0xffc00000	/* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE		4		/* flash size in MB */
 #define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | \
-					 (2 << BR_PS_SHIFT) |	/*  32bit */ \
+					 (2 << BR_PS_SHIFT) |	/*  16bit */ \
 					 BR_V)			/* valid */
 
 #define CONFIG_SYS_OR0_PRELIM		0xffc06ff7	/*   4 MB flash size */
@@ -128,7 +128,7 @@
 #define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE		128		/* flash size in MB */
 #define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | \
-					 (2 << BR_PS_SHIFT) |	/*  32bit */ \
+					 (2 << BR_PS_SHIFT) |	/*  16bit */ \
 					 BR_V)			/* valid */
 
 #define CONFIG_SYS_OR0_PRELIM		0xf8006ff7	/* 128 MB flash size */
diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h
index 0dde65d..d46717c 100644
--- a/include/configs/voiceblue.h
+++ b/include/configs/voiceblue.h
@@ -31,8 +31,8 @@
 #define CONFIG_OMAP1510 1		/* which is in a 5910 */
 
 /* Input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	150000000	/* 150MHz input clock */
-#define CONFIG_XTAL_FREQ	12000000
+#define CONFIG_SYS_CLK_FREQ		150000000	/* 150MHz */
+#define CONFIG_XTAL_FREQ		12000000	/*  12MHz */
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
@@ -48,55 +48,53 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	(64 * 1024 * 1024)
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x10000000
+#define PHYS_SDRAM_1_SIZE		(64 * 1024 * 1024)
+#define PHYS_FLASH_1			0x0000000
 
-#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1 */
-
-#define CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1 + 0x400000	/* default load address */
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI			/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER		/* Use the common driver */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-
-/* FIXME: Does not work on AMD flash */
-/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */	/* use buffered writes (20x faster) */
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max # of sectors on one chip */
-
-#define CONFIG_SYS_MONITOR_BASE	PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
 
 /*
  * Environment settings
  */
 #define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE		(8 * 1024)
-#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
 
 #define CONFIG_ENV_OVERWRITE
 
 /*
  * Size of malloc() pool and stack
  */
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-#define CONFIG_STACKSIZE	(1 * 1024 * 1024)
-#define PHYS_SDRAM_1_RESERVED	(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)
+#define CONFIG_STACKSIZE		(1 * 1024 * 1024)
 
 /*
  * Hardware drivers
  */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(CONFIG_XTAL_FREQ)
+#define CONFIG_SYS_NS16550_COM1		OMAP1510_UART1_BASE
+
 #define CONFIG_NET_MULTI
 #define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE	0x08000300
+#define CONFIG_SMC91111_BASE		0x08000300
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 #define CONFIG_HARD_I2C
 #define CONFIG_SYS_I2C_SPEED		100000
@@ -104,24 +102,16 @@
 #define CONFIG_DRIVER_OMAP1510_I2C
 
 #define CONFIG_RTC_DS1307
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
 
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		(CONFIG_XTAL_FREQ)	/* can be 12M/32Khz or 48Mhz  */
-#define CONFIG_SYS_NS16550_COM1	OMAP1510_UART1_BASE	/* uart1 */
 
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_BAUDRATE		115200
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 
 /*
- * Command line configuration.
+ * Command line configuration
  */
 #include <config_cmd_default.h>
 
@@ -138,7 +128,6 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_RUN
 
-
 /*
  * BOOTP options
  */
@@ -147,36 +136,39 @@
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_BOOTPATH
 
-
 #define CONFIG_LOOPW
 
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow to break in always */
-#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs*/
-#define CONFIG_SYS_AUTOLOAD		"n"		/* No autoload */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs*/
+#define CONFIG_SYS_AUTOLOAD		"n"
 #define CONFIG_BOOTCOMMAND	"run nboot"
 #define CONFIG_PREBOOT		"run setup"
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-	"silent=1\0"						\
-	"ospart=0\0"						\
-	"bootfile=/boot/uImage\0"				\
-	"setpart="						\
-	"if test -n $swapos; then "				\
-		"setenv swapos; saveenv; "			\
-		"if test $ospart -eq 0; then setenv ospart 1; else setenv ospart 0; fi; "\
-	"fi\0"							\
-	"setup=setenv bootargs console=ttyS0,$baudrate "	\
-		"mtdparts=$mtdparts\0"				\
-	"nfsargs=setenv bootargs $bootargs "			\
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"silent=1\0"							\
+	"ospart=0\0"							\
+	"bootfile=/boot/uImage\0"					\
+	"setpart="							\
+	"if test -n $swapos; then "					\
+		"setenv swapos; saveenv; "				\
+		"if test $ospart -eq 0; then "				\
+			"setenv ospart 1; "				\
+		"else "							\
+			"setenv ospart 0; "				\
+		"fi; "							\
+	"fi\0"								\
+	"setup=setenv bootargs console=ttyS0,$baudrate "		\
+		"mtdparts=$mtdparts\0"					\
+	"nfsargs=setenv bootargs $bootargs "				\
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
-		"nfsroot=$rootpath root=/dev/nfs\0"		\
-	"flashargs=run setpart; setenv bootargs $bootargs "	\
-		"root=mtd:data$ospart ro "			\
-		"rootfstype=jffs2\0"				\
-	"initrdargs=setenv bootargs $bootargs "			\
+		"nfsroot=$rootpath root=/dev/nfs\0"			\
+	"flashargs=run setpart; setenv bootargs $bootargs "		\
+		"root=mtd:data$ospart ro "				\
+		"rootfstype=jffs2\0"					\
+	"initrdargs=setenv bootargs $bootargs "				\
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
-	"fboot=run flashargs; chpart data$ospart; fsload; bootm\0" \
-	"mboot=bootp; run initrdargs; tftp; bootm\0"		\
+	"fboot=run flashargs; chpart data$ospart; fsload; bootm\0"	\
+	"mboot=bootp; run initrdargs; tftp; bootm\0"			\
 	"nboot=bootp; run nfsargs; tftp; bootm\0"
 
 #define CONFIG_SILENT_CONSOLE		1	/* enable silent startup */
@@ -188,14 +180,14 @@
 #endif
 
 /*
- * JFFS2 partitions (mtdparts command line support)
+ * Partitions (mtdparts command line support)
  */
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
 #define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=omapflash.0"
-#define MTDPARTS_DEFAULT	"mtdparts=omapflash.0:256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)"
-
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:" \
+	"256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)"
 
 /*
  * Miscellaneous configurable options
@@ -203,26 +195,30 @@
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT		"# "		/* Monitor Command Prompt	*/
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - PHYS_SDRAM_1_RESERVED
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"# "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1)
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
+	(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE))
+#define CONFIG_SYS_LOAD_ADDR		(PHYS_SDRAM_1 + 0x400000)
 
-/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
+/*
+ * The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
  * This time is further subdivided by a local divisor.
  */
-#define CONFIG_SYS_TIMERBASE	OMAP1510_TIMER1_BASE
-#define CONFIG_SYS_PTV		7	/* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_TIMERBASE		OMAP1510_TIMER1_BASE
+#define CONFIG_SYS_PTV			7	/* 2^(PTV+1), divide by 256 */
+#define CONFIG_SYS_HZ			1000
 
-#define OMAP5910_DPLL_DIV	1
-#define OMAP5910_DPLL_MUL	((CONFIG_SYS_CLK_FREQ * \
-				 (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
+#define OMAP5910_DPLL_DIV		1
+#define OMAP5910_DPLL_MUL		\
+	((CONFIG_SYS_CLK_FREQ * (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
 
 #define OMAP5910_ARM_PER_DIV	2	/* CKL/4 */
 #define OMAP5910_LCD_DIV	2	/* CKL/4 */
author	Minkyu Kang <mk7.kang@samsung.com>	2010-03-15 10:51:36 +0900
committer	Minkyu Kang <mk7.kang@samsung.com>	2010-03-15 10:51:36 +0900
commit	995a4b1d83a08223c82c1e15778b02e85e5bba51 (patch)
tree	0acb85278216df76d8fb7284b32d6dd95a1fc978 /include/configs
parent	a8d25fc26f681a9c4dfb062ebb4b00b9509a7966 (diff)
parent	44de3e8ff7ed48bf96ec6c5e2173187d9c1c61e6 (diff)
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